soc/amd/picasso: Remove ST files not used for PCO
Remove files that aren't needed for the picasso port. Remove traces of AGESA v5 (includes binaryPI support files). Remove SPD helper. Picasso (and all AMD Family 17h processors) have a very different boot flow from previous products. Memory is initialized by the PSP before the x86 processor is released from reset. The SPD is read by the PSP, so it's not needed in coreboot. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I743ffd6058982f8f182ea4d73172a029967f3ea5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This commit is contained in:
Martin Roth
Martin Roth
parent
5c354b9979
commit
360035ee5b
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@ -1,166 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011, 2017 Advanced Micro Devices, Inc.
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* Copyright (C) 2013 Sage Electronic Engineering, LLC
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* Copyright (C) 2017 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/device.h>
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#include <device/pci_def.h>
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#include <amdblocks/BiosCallOuts.h>
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#include <console/console.h>
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#include <soc/southbridge.h>
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#include <soc/pci_devs.h>
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#include <stdlib.h>
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#include <amdblocks/agesawrapper.h>
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#include <amdblocks/dimm_spd.h>
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#include <amdblocks/car.h>
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#include "chip.h"
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void __weak platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset) {}
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AGESA_STATUS agesa_fch_initreset(uint32_t Func, uintptr_t FchData,
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void *ConfigPtr)
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{
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AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
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if (StdHeader->Func == AMD_INIT_RESET) {
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FCH_RESET_DATA_BLOCK *FchParams_reset;
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FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
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printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
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/* Get platform specific configuration changes */
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platform_FchParams_reset(FchParams_reset);
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printk(BIOS_DEBUG, "Done\n");
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}
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return AGESA_SUCCESS;
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}
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AGESA_STATUS agesa_fch_initenv(uint32_t Func, uintptr_t FchData,
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void *ConfigPtr)
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{
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AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
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const struct device *dev = pcidev_path_on_root(SATA_DEVFN);
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if (StdHeader->Func == AMD_INIT_ENV) {
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FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
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printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
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/* XHCI configuration */
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if (CONFIG(STONEYRIDGE_XHCI_ENABLE))
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FchParams_env->Usb.Xhci0Enable = TRUE;
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else
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FchParams_env->Usb.Xhci0Enable = FALSE;
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FchParams_env->Usb.Xhci1Enable = FALSE;
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/* SATA configuration */
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FchParams_env->Sata.SataClass = CONFIG_STONEYRIDGE_SATA_MODE;
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if (dev && dev->enabled) {
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switch ((SATA_CLASS)CONFIG_STONEYRIDGE_SATA_MODE) {
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case SataRaid:
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case SataAhci:
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case SataAhci7804:
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case SataLegacyIde:
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FchParams_env->Sata.SataIdeMode = FALSE;
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break;
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case SataIde2Ahci:
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case SataIde2Ahci7804:
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default: /* SataNativeIde */
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FchParams_env->Sata.SataIdeMode = TRUE;
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break;
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}
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} else
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FchParams_env->Sata.SataIdeMode = FALSE;
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/* Platform updates */
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platform_FchParams_env(FchParams_env);
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printk(BIOS_DEBUG, "Done\n");
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}
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return AGESA_SUCCESS;
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}
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AGESA_STATUS agesa_ReadSpd(uint32_t Func, uintptr_t Data, void *ConfigPtr)
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{
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uint8_t spd_address;
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int err;
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DEVTREE_CONST struct device *dev;
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DEVTREE_CONST struct soc_amd_stoneyridge_config *conf;
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AGESA_READ_SPD_PARAMS *info = ConfigPtr;
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if (!ENV_ROMSTAGE)
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return AGESA_UNSUPPORTED;
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dev = pcidev_path_on_root(DCT_DEVFN);
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if (dev == NULL)
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return AGESA_ERROR;
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conf = dev->chip_info;
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if (conf == NULL)
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return AGESA_ERROR;
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if (info->SocketId >= ARRAY_SIZE(conf->spd_addr_lookup))
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return AGESA_ERROR;
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if (info->MemChannelId >= ARRAY_SIZE(conf->spd_addr_lookup[0]))
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return AGESA_ERROR;
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if (info->DimmId >= ARRAY_SIZE(conf->spd_addr_lookup[0][0]))
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return AGESA_ERROR;
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spd_address = conf->spd_addr_lookup
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[info->SocketId][info->MemChannelId][info->DimmId];
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if (spd_address == 0)
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return AGESA_ERROR;
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err = mainboard_read_spd(spd_address, (void *)info->Buffer,
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CONFIG_DIMM_SPD_SIZE);
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/* Read the SPD if the mainboard didn't fill the buffer */
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if (err || (*info->Buffer == 0))
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err = sb_read_spd(spd_address, (void *)info->Buffer,
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CONFIG_DIMM_SPD_SIZE);
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if (err)
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return AGESA_ERROR;
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return AGESA_SUCCESS;
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}
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AGESA_STATUS agesa_HaltThisAp(uint32_t Func, uintptr_t Data, void *ConfigPtr)
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{
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AGESA_HALT_THIS_AP_PARAMS *info = ConfigPtr;
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uint32_t flags = 0;
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if (info->PrimaryCore == TRUE)
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return AGESA_UNSUPPORTED; /* force normal path */
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if (info->ExecWbinvd == TRUE)
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flags |= 1;
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if (info->CacheEn == TRUE)
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flags |= 2;
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ap_teardown_car(flags); /* does not return */
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/* Should never reach here */
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return AGESA_UNSUPPORTED;
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}
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/* Allow mainboards to fill the SPD buffer */
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__weak int mainboard_read_spd(uint8_t spdAddress, char *buf,
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size_t len)
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{
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printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
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return -1; /* SPD not read */
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}
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@ -1,42 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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// Use simple device model for this file even in ramstage
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#define __SIMPLE_DEVICE__
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#include <stdint.h>
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#include <device/pci_ops.h>
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#include <device/pci_ehci.h>
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#include <device/pci_def.h>
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#include <soc/pci_devs.h>
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#include <soc/southbridge.h>
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pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
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{
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pm_io_write8(PM_USB_ENABLE, PM_USB_ALL_CONTROLLERS);
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return SOC_EHCI1_DEV;
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}
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void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
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{
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u32 reg32, value;
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value = (port & 0x3) << DEBUG_PORT_SELECT_SHIFT;
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value |= DEBUG_PORT_ENABLE;
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reg32 = pci_read_config32(SOC_EHCI1_DEV, EHCI_HUB_CONFIG4);
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reg32 &= ~DEBUG_PORT_MASK;
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reg32 |= value;
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pci_write_config32(SOC_EHCI1_DEV, EHCI_HUB_CONFIG4, reg32);
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}
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@ -38,35 +38,28 @@ subdirs-y += ../../../cpu/x86/pae
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subdirs-y += ../../../cpu/x86/smm
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bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c
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bootblock-y += BiosCallOuts.c
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bootblock-y += bootblock/bootblock.c
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bootblock-y += gpio.c
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bootblock-y += i2c.c
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bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c
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bootblock-y += monotonic_timer.c
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bootblock-y += pmutil.c
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bootblock-y += reset.c
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bootblock-y += tsc_freq.c
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bootblock-y += southbridge.c
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bootblock-y += nb_util.c
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bootblock-$(CONFIG_SPI_FLASH) += spi.c
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bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
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romstage-y += BiosCallOuts.c
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romstage-y += i2c.c
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romstage-y += romstage.c
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romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
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romstage-y += gpio.c
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romstage-y += monotonic_timer.c
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romstage-y += pmutil.c
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romstage-y += reset.c
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romstage-y += smbus.c
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romstage-y += smbus_spd.c
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romstage-y += ramtop.c
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romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
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romstage-y += tsc_freq.c
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romstage-y += southbridge.c
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romstage-y += nb_util.c
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romstage-$(CONFIG_SPI_FLASH) += spi.c
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romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
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@ -77,22 +70,18 @@ verstage-y += pmutil.c
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verstage-y += reset.c
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verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
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verstage-y += tsc_freq.c
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verstage-y += nb_util.c
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verstage-$(CONFIG_SPI_FLASH) += spi.c
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postcar-y += monotonic_timer.c
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postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c
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postcar-y += ramtop.c
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postcar-y += nb_util.c
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postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c
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postcar-y += tsc_freq.c
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ramstage-y += BiosCallOuts.c
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ramstage-y += i2c.c
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ramstage-y += chip.c
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ramstage-y += cpu.c
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ramstage-y += mca.c
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ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
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ramstage-y += gpio.c
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ramstage-y += monotonic_timer.c
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@ -111,7 +100,6 @@ ramstage-y += usb.c
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ramstage-y += tsc_freq.c
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ramstage-$(CONFIG_SPI_FLASH) += spi.c
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ramstage-y += finalize.c
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ramstage-y += nb_util.c
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smm-y += monotonic_timer.c
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smm-y += smihandler.c
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@ -119,7 +107,6 @@ smm-y += smi_util.c
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smm-y += tsc_freq.c
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smm-$(CONFIG_DEBUG_SMI) += uart.c
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smm-$(CONFIG_SPI_FLASH) += spi.c
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smm-y += nb_util.c
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smm-y += gpio.c
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CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge
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@ -1,40 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Advanced Micro Devices
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <soc/northbridge.h>
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#include <soc/pci_devs.h>
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#include <device/pci_ops.h>
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uint32_t nb_ioapic_read(unsigned int index)
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{
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pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index);
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return pci_read_config32(SOC_GNB_DEV, NB_IOAPIC_DATA);
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}
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void nb_ioapic_write(unsigned int index, uint32_t value)
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{
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pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index);
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pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, value);
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}
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void *get_ap_entry_ptr(void)
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{
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return (void *)nb_ioapic_read(AP_SCRATCH_REG);
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}
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void set_ap_entry_ptr(void *entry)
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{
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nb_ioapic_write(AP_SCRATCH_REG, (uintptr_t)entry);
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}
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@ -1,76 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012, 2017 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <amdblocks/agesawrapper.h>
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#include <console/console.h>
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#include <device/pci_def.h>
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#include <device/device.h>
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#include <soc/southbridge.h>
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#include <soc/smbus.h>
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#include <amdblocks/dimm_spd.h>
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/*
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* readspd - Read one or more SPD bytes from a DIMM.
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* Start with offset zero and read sequentially.
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* Optimization relies on autoincrement to avoid
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* sending offset for every byte.
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* Reads 128 bytes in 7-8 ms at 400 KHz.
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*/
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static int readspd(uint8_t SmbusSlaveAddress, char *buffer, size_t count)
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{
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uint8_t dev_addr;
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size_t index;
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int error;
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char *pbuf = buffer;
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printk(BIOS_SPEW, "-------------READING SPD-----------\n");
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printk(BIOS_SPEW, "SmbusSlave: 0x%08X, count: %zd\n",
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SmbusSlaveAddress, count);
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/*
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* Convert received device address to the format accepted by
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* do_smbus_read_byte and do_smbus_recv_byte.
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*/
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dev_addr = (SmbusSlaveAddress >> 1);
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/* Read the first SPD byte */
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error = do_smbus_read_byte(ACPIMMIO_SMBUS_BASE, dev_addr, 0);
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if (error < 0) {
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printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n");
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return error;
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}
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*pbuf = (char) error;
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pbuf++;
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/* Read the remaining SPD bytes using do_smbus_recv_byte for speed */
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for (index = 1 ; index < count ; index++) {
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error = do_smbus_recv_byte(ACPIMMIO_SMBUS_BASE, dev_addr);
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if (error < 0) {
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printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n");
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return error;
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}
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*pbuf = (char) error;
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pbuf++;
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}
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printk(BIOS_SPEW, "\n");
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printk(BIOS_SPEW, "-------------FINISHED READING SPD-----------\n");
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return 0;
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}
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int sb_read_spd(uint8_t spdAddress, char *buf, size_t len)
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{
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return readspd(spdAddress, buf, len);
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}
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