mb/hp/z220_series: Convert z220_sff_workstation into variant

No functional change, just refactoring to make room for CMT variant.

Built with BUILD_TIMELESS=1 and no config included before and after.
	$ diff master.rom build/coreboot.rom
	$

TESTED: boots to SeaBIOS on HP Z220 SFF

Flashed bios region internally, mainboard also has FDO
(flash descriptor override) jumper that allows r/w to whole flash.

Change-Id: I6aaac75216b2d7c8bb48801454ce616ace3b1422
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Damien Zammit 2022-03-15 19:29:23 +11:00 committed by Felix Held
parent 311ddf3b81
commit 3605dac10b
18 changed files with 32 additions and 9 deletions

View File

@ -1,7 +1,5 @@
if BOARD_HP_Z220_SFF_WORKSTATION
config BOARD_SPECIFIC_OPTIONS
def_bool y
config BOARD_HP_Z220_SERIES_COMMON
def_bool n
select BOARD_ROMSIZE_KB_16384
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
@ -20,6 +18,11 @@ config BOARD_SPECIFIC_OPTIONS
select GFX_GMA_ANALOG_I2C_HDMI_B
select MAINBOARD_USES_IFD_GBE_REGION
config BOARD_HP_Z220_SFF_WORKSTATION
select BOARD_HP_Z220_SERIES_COMMON
if BOARD_HP_Z220_SERIES_COMMON
config VBOOT
select VBOOT_VBNV_CMOS
select VBOOT_NO_BOARD_SUPPORT
@ -36,10 +39,19 @@ config CBFS_SIZE
default 0x570000
config MAINBOARD_DIR
default "hp/z220_sff_workstation"
default "hp/z220_series"
config VARIANT_DIR
default "z220_sff_workstation" if BOARD_HP_Z220_SFF_WORKSTATION
config MAINBOARD_PART_NUMBER
default "HP Z220 SFF Workstation"
default "HP Z220 SFF Workstation" if BOARD_HP_Z220_SFF_WORKSTATION
config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
config INTEL_GMA_VBT_FILE
default "src/mainboard/\$(MAINBOARDDIR)/data.vbt"
config DRAM_RESET_GATE_GPIO
int

View File

@ -1,5 +1,5 @@
bootblock-y += gpio.c
romstage-y += gpio.c
bootblock-y += variants/$(VARIANT_DIR)/gpio.c
romstage-y += variants/$(VARIANT_DIR)/gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

View File

@ -30,7 +30,6 @@ chip northbridge/intel/sandybridge
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "true"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0xf"
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"

View File

@ -0,0 +1,12 @@
## SPDX-License-Identifier: GPL-2.0-only
chip northbridge/intel/sandybridge
device domain 0 on
subsystemid 0x103c 0x1791 inherit
chip southbridge/intel/bd82x6x
register "sata_port_map" = "0xf"
device pci 1c.4 on end # dummy setting
end
end
end