diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index bdd6e8c9d9..d14dd8d3ee 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -73,23 +73,6 @@ static void soc_early_romstage_init(void) P2SB_HPTC_ADDRESS_ENABLE); } -/* Thermal throttle activation offset */ -static void configure_thermal_target(void) -{ - msr_t msr; - const config_t *conf = config_of_soc(); - - if (!conf->tcc_offset) - return; - - msr = rdmsr(MSR_TEMPERATURE_TARGET); - /* Bits 27:24 */ - msr.lo &= ~(TEMPERATURE_TCC_MASK << TEMPERATURE_TCC_SHIFT); - msr.lo |= (conf->tcc_offset & TEMPERATURE_TCC_MASK) - << TEMPERATURE_TCC_SHIFT; - wrmsr(MSR_TEMPERATURE_TARGET, msr); -} - /* * Punit Initialization code. This all isn't documented, but * this is the recipe. @@ -101,7 +84,7 @@ static bool punit_init(void) struct stopwatch sw; /* Thermal throttle activation offset */ - configure_thermal_target(); + configure_tcc_thermal_target(); /* * Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR). diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 4bfa15d354..1312525814 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -290,22 +290,6 @@ static void configure_c_states(void) wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); } -static void configure_thermal_target(void) -{ - config_t *conf = config_of_soc(); - msr_t msr; - - - /* Set TCC activation offset if supported */ - msr = rdmsr(MSR_PLATFORM_INFO); - if ((msr.lo & (1 << 30)) && conf->tcc_offset) { - msr = rdmsr(MSR_TEMPERATURE_TARGET); - msr.lo &= ~(0xf << 24); /* Bits 27:24 */ - msr.lo |= (conf->tcc_offset & 0xf) << 24; - wrmsr(MSR_TEMPERATURE_TARGET, msr); - } -} - static void configure_misc(void) { msr_t msr; @@ -430,7 +414,7 @@ static void cpu_core_init(struct device *cpu) configure_misc(); /* Thermal throttle activation offset */ - configure_thermal_target(); + configure_tcc_thermal_target(); /* Enable Direct Cache Access */ configure_dca_cap(); diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 89d3493889..36d252e477 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -155,25 +155,6 @@ static void configure_c_states(void) wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); } -static void configure_thermal_target(void) -{ - config_t *conf = config_of_soc(); - msr_t msr; - - /* Set TCC activation offset if supported */ - msr = rdmsr(MSR_PLATFORM_INFO); - if ((msr.lo & (1 << 30)) && conf->tcc_offset) { - msr = rdmsr(MSR_TEMPERATURE_TARGET); - msr.lo &= ~(0xf << 24); /* Bits 27:24 */ - msr.lo |= (conf->tcc_offset & 0xf) << 24; - wrmsr(MSR_TEMPERATURE_TARGET, msr); - } - msr = rdmsr(MSR_TEMPERATURE_TARGET); - msr.lo &= ~0x7f; /* Bits 6:0 */ - msr.lo |= 0xe6; /* setting 100ms thermal time window */ - wrmsr(MSR_TEMPERATURE_TARGET, msr); -} - /* * The emulated ACPI timer allows replacing of the ACPI timer * (PM1_TMR) to have no impart on the system. @@ -282,7 +263,7 @@ void soc_init_cpus(struct bus *cpu_bus) printk(BIOS_ERR, "MP initialization failure.\n"); /* Thermal throttle activation offset */ - configure_thermal_target(); + configure_tcc_thermal_target(); } int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index dac654fea6..0ac8dda1a4 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -8,6 +8,7 @@ #include #include #include +#include #include /* @@ -254,6 +255,26 @@ uint32_t cpu_get_max_ratio(void) return ratio_max; } +void configure_tcc_thermal_target(void) +{ + const config_t *conf = config_of_soc(); + msr_t msr; + + /* Set TCC activation offset */ + msr = rdmsr(MSR_PLATFORM_INFO); + if ((msr.lo & BIT(30)) && conf->tcc_offset) { + msr = rdmsr(MSR_TEMPERATURE_TARGET); + msr.lo &= ~(0xf << 24); + msr.lo |= (conf->tcc_offset & 0xf) << 24; + wrmsr(MSR_TEMPERATURE_TARGET, msr); + } + msr = rdmsr(MSR_TEMPERATURE_TARGET); + /* Time Window Tau Bits [6:0] */ + msr.lo &= ~0x7f; + msr.lo |= 0xe6; /* setting 100ms thermal time window */ + wrmsr(MSR_TEMPERATURE_TARGET, msr); +} + uint32_t cpu_get_bus_clock(void) { /* CPU bus clock is set by default here to 100MHz. diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index 73f4e38332..09f5e45577 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -133,6 +133,9 @@ uint32_t cpu_get_min_ratio(void); */ uint32_t cpu_get_max_ratio(void); +/* Thermal throttle activation offset */ +void configure_tcc_thermal_target(void); + /* * cpu_get_power_max calculates CPU TDP in mW */ diff --git a/src/soc/intel/denverton_ns/chip.h b/src/soc/intel/denverton_ns/chip.h index 8401eb1a6f..2f16bf554e 100644 --- a/src/soc/intel/denverton_ns/chip.h +++ b/src/soc/intel/denverton_ns/chip.h @@ -56,6 +56,9 @@ struct soc_intel_denverton_ns_config { uint32_t ipc1; uint32_t ipc2; uint32_t ipc3; + + /* TCC activation offset */ + uint32_t tcc_offset; }; typedef struct soc_intel_denverton_ns_config config_t; diff --git a/src/soc/intel/denverton_ns/include/soc/soc_chip.h b/src/soc/intel/denverton_ns/include/soc/soc_chip.h new file mode 100644 index 0000000000..800e78e7d1 --- /dev/null +++ b/src/soc/intel/denverton_ns/include/soc/soc_chip.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DENVERTON_NS_SOC_CHIP_H_ +#define _SOC_DENVERTON_NS_SOC_CHIP_H_ + +#include "../../chip.h" + +#endif /* _SOC_DENVERTON_NS_SOC_CHIP_H_ */ diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index a545435599..d941df70b2 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -27,26 +27,6 @@ #include "chip.h" -static void configure_thermal_target(void) -{ - config_t *conf = config_of_soc(); - msr_t msr; - - - /* Set TCC activation offset if supported */ - msr = rdmsr(MSR_PLATFORM_INFO); - if ((msr.lo & (1 << 30)) && conf->tcc_offset) { - msr = rdmsr(MSR_TEMPERATURE_TARGET); - msr.lo &= ~(0xf << 24); /* Bits 27:24 */ - msr.lo |= (conf->tcc_offset & 0xf) << 24; - wrmsr(MSR_TEMPERATURE_TARGET, msr); - } - msr = rdmsr(MSR_TEMPERATURE_TARGET); - msr.lo &= ~0x7f; /* Bits 6:0 */ - msr.lo |= 0xe6; /* setting 100ms thermal time window */ - wrmsr(MSR_TEMPERATURE_TARGET, msr); -} - static void configure_isst(void) { config_t *conf = config_of_soc(); @@ -333,7 +313,7 @@ void soc_init_cpus(struct bus *cpu_bus) printk(BIOS_ERR, "MP initialization failure.\n"); /* Thermal throttle activation offset */ - configure_thermal_target(); + configure_tcc_thermal_target(); } int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) diff --git a/src/soc/intel/xeon_sp/cpx/chip.h b/src/soc/intel/xeon_sp/cpx/chip.h index 6bf7272572..61e806e473 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.h +++ b/src/soc/intel/xeon_sp/cpx/chip.h @@ -67,6 +67,9 @@ struct soc_intel_xeon_sp_cpx_config { uint32_t gen2_dec; uint32_t gen3_dec; uint32_t gen4_dec; + + /* TCC activation offset */ + uint32_t tcc_offset; }; typedef struct soc_intel_xeon_sp_cpx_config config_t; diff --git a/src/soc/intel/xeon_sp/include/soc/soc_chip.h b/src/soc/intel/xeon_sp/include/soc/soc_chip.h new file mode 100644 index 0000000000..3113eadf55 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/soc_chip.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_XEON_SP_SOC_CHIP_H_ +#define _SOC_XEON_SP_SOC_CHIP_H_ + +#include "../chip.h" + +#endif /* _SOC_XEON_SP_SOC_CHIP_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/chip.h b/src/soc/intel/xeon_sp/skx/chip.h index c7f19ec811..440fb40f3d 100644 --- a/src/soc/intel/xeon_sp/skx/chip.h +++ b/src/soc/intel/xeon_sp/skx/chip.h @@ -69,6 +69,9 @@ struct soc_intel_xeon_sp_skx_config { uint32_t gen2_dec; uint32_t gen3_dec; uint32_t gen4_dec; + + /* TCC activation offset */ + uint32_t tcc_offset; }; typedef struct soc_intel_xeon_sp_skx_config config_t;