nb/intel/sandybridge: Move to C_ENVIRONMENT_BOOTBLOCK

There is some overlap between romstage and bootblock.
LPC setup and BAR initialization is now done twice.
The rationale is that the romstage should not depend too
much on the bootblock, since it can reside in a RO fmap
region.

Enabling the console will be done in a followup patch.

Change-Id: I4d0ba29111a5df6f19033f5ce95adcc0d9adc1fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/cpu/intel/model_206ax/Kconfig

@@ -21,10 +21,8 @@ config CPU_SPECIFIC_OPTIONS
 	select CPU_INTEL_COMMON_TIMEBASE
 	select PARALLEL_MP
 	select NO_FIXED_XIP_ROM_SIZE
-
-config BOOTBLOCK_CPU_INIT
-	string
-	default "cpu/intel/model_206ax/bootblock.c"
+	select C_ENVIRONMENT_BOOTBLOCK
+	select NO_BOOTBLOCK_CONSOLE
 
 config SMM_TSEG_SIZE
 	hex

src/cpu/intel/model_206ax/Makefile.inc

@@ -21,7 +21,11 @@ smm-y += finalize.c
 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-2a-*)
 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3a-*)
 
-cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
+bootblock-y += bootblock.c
+bootblock-y += ../car/non-evict/cache_as_ram.S
+bootblock-y += ../../x86/early_reset.S
+bootblock-y += ../car/bootblock.c
+
 postcar-y += ../car/non-evict/exit_car.S
 
 romstage-y += ../car/romstage.c

src/cpu/intel/model_206ax/bootblock.c

@@ -13,13 +13,11 @@
 
 #include <stdint.h>
 #include <arch/cpu.h>
-#include <cpu/x86/cache.h>
 #include <cpu/x86/msr.h>
-#include <cpu/x86/mtrr.h>
 #include <arch/io.h>
 #include <halt.h>
+#include <cpu/intel/car/bootblock.h>
 
-#include <cpu/intel/microcode/microcode.c>
 #include "model_206ax.h"
 
 #if CONFIG(SOUTHBRIDGE_INTEL_BD82X6X) || \
@@ -30,35 +28,6 @@
 #error "CPU must be paired with Intel BD82X6X or C216 southbridge"
 #endif
 
-static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size,
-	unsigned int type)
-
-{
-	/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
-	/* FIXME: It only support 4G less range */
-	msr_t basem, maskm;
-	basem.lo = base | type;
-	basem.hi = 0;
-	wrmsr(MTRR_PHYS_BASE(reg), basem);
-	maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
-	maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
-	wrmsr(MTRR_PHYS_MASK(reg), maskm);
-}
-
-static void enable_rom_caching(void)
-{
-	msr_t msr;
-
-	disable_cache();
-	set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
-	enable_cache();
-
-	/* Enable Variable MTRRs */
-	msr.hi = 0x00000000;
-	msr.lo = 0x00000800;
-	wrmsr(MTRR_DEF_TYPE_MSR, msr);
-}
-
 static void set_flex_ratio_to_tdp_nominal(void)
 {
 	msr_t flex_ratio, msr;
@@ -109,10 +78,8 @@ static void set_flex_ratio_to_tdp_nominal(void)
 	halt();
 }
 
-static void bootblock_cpu_init(void)
+void bootblock_early_cpu_init(void)
 {
 	/* Set flex ratio and reset if needed */
 	set_flex_ratio_to_tdp_nominal();
-	enable_rom_caching();
-	intel_update_microcode_from_cbfs();
 }

src/mainboard/apple/macbookair4_2/Makefile.inc

@@ -1,3 +1,4 @@
+bootblock-y += gpio.c
 romstage-y += gpio.c
 ramstage-y += gnvs.c
 

src/mainboard/asrock/b75pro3-m/Makefile.inc

@@ -13,6 +13,7 @@
 ## GNU General Public License for more details.
 ##
 
+bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/asus/h61m-cs/Makefile.inc

@@ -1,2 +1,3 @@
+bootblock-y += gpio.c
 romstage-y += gpio.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/asus/maximus_iv_gene-z/Makefile.inc

@@ -14,5 +14,6 @@
 ## GNU General Public License for more details.
 ##
 
+bootblock-y += gpio.c
 romstage-y += gpio.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/asus/p8h61-m_lx/Makefile.inc

@@ -14,5 +14,6 @@
 ## GNU General Public License for more details.
 ##
 
+bootblock-y += gpio.c
 romstage-y += gpio.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/asus/p8h61-m_pro/Makefile.inc

@@ -1,3 +1,4 @@
+bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/asus/p8z77-m_pro/Makefile.inc

@@ -14,6 +14,7 @@
 ## GNU General Public License for more details.
 ##
 
+bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/compulab/intense_pc/Makefile.inc

@@ -1,3 +1,4 @@
+bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc

@@ -13,6 +13,7 @@
 ## GNU General Public License for more details.
 ##
 
+bootblock-y += variants/$(VARIANT_DIR)/gpio.c
 romstage-y += variants/$(VARIANT_DIR)/gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads

src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc

@@ -1,3 +1,4 @@
+bootblock-y += variants/$(VARIANT_DIR)/gpio.c
 romstage-y += variants/$(VARIANT_DIR)/gpio.c
 
 ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c

src/mainboard/google/butterfly/Makefile.inc

@@ -17,6 +17,7 @@ ramstage-y += ec.c
 
 romstage-y += chromeos.c
 ramstage-y += chromeos.c
+bootblock-y += gpio.c
 romstage-y += gpio.c
 
 smm-y += mainboard_smi.c

src/mainboard/google/link/Makefile.inc

@@ -40,4 +40,5 @@ $(SPD_BIN): $(SPD_DEPS)
 cbfs-files-y += spd.bin
 spd.bin-file := $(SPD_BIN)
 spd.bin-type := spd
+bootblock-y += gpio.c
 romstage-y += gpio.c

src/mainboard/google/parrot/Makefile.inc

@@ -17,6 +17,7 @@ ramstage-y += ec.c
 
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/google/stout/Makefile.inc

@@ -22,6 +22,7 @@ smm-y += mainboard_smi.c
 smm-y += ec.c
 
 SRC_ROOT = $(src)/mainboard/google/stout
+bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/hp/2570p/Makefile.inc

@@ -13,6 +13,7 @@
 ## GNU General Public License for more details.
 ##
 
+bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/hp/2760p/Makefile.inc

@@ -13,6 +13,7 @@
 ## GNU General Public License for more details.
 ##
 
+bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/hp/8460p/Makefile.inc

@@ -13,6 +13,7 @@
 ## GNU General Public License for more details.
 ##
 
+bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/hp/8470p/Makefile.inc

@@ -13,6 +13,7 @@
 ## GNU General Public License for more details.
 ##
 
+bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/hp/8770w/Makefile.inc

@@ -13,4 +13,5 @@
 ## GNU General Public License for more details.
 ##
 
+bootblock-y += gpio.c
 romstage-y += gpio.c

src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc

@@ -1,2 +1,3 @@
+bootblock-y += gpio.c
 romstage-y += gpio.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/hp/folio_9470m/Makefile.inc

@@ -13,6 +13,7 @@
 ## GNU General Public License for more details.
 ##
 
+bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/hp/revolve_810_g1/Makefile.inc

@@ -13,6 +13,7 @@
 ## GNU General Public License for more details.
 ##
 
+bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/hp/z220_sff_workstation/Makefile.inc

@@ -1,2 +1,3 @@
+bootblock-y += gpio.c
 romstage-y += gpio.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/intel/dcp847ske/Makefile.inc

@@ -1,4 +1,5 @@
 romstage-y += early_southbridge.c
+bootblock-y += gpio.c
 romstage-y += gpio.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
 smm-y += smihandler.c

src/mainboard/intel/emeraldlake2/Makefile.inc

@@ -15,4 +15,5 @@
 
 romstage-y += chromeos.c
 ramstage-y += chromeos.c
+bootblock-y += gpio.c
 romstage-y += gpio.c

src/mainboard/kontron/ktqm77/Makefile.inc

@@ -1,3 +1,4 @@
+bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/lenovo/l520/Makefile.inc

@@ -14,6 +14,7 @@
 ##
 
 romstage-y += romstage.c
+bootblock-y += gpio.c
 romstage-y += gpio.c
 smm-y += smihandler.c
 

src/mainboard/lenovo/s230u/Makefile.inc

@@ -1,3 +1,4 @@
+bootblock-y += gpio.c
 romstage-y += gpio.c
 ramstage-y += ec.c
 smm-y += smihandler.c

src/mainboard/lenovo/t420/Makefile.inc

@@ -14,6 +14,7 @@
 ##
 
 smm-y += smihandler.c
+bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/lenovo/t420s/Makefile.inc

@@ -14,6 +14,7 @@
 ##
 
 smm-y += smihandler.c
+bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/lenovo/t430/Makefile.inc

@@ -1,4 +1,5 @@
 romstage-y += romstage.c
+bootblock-y += gpio.c
 romstage-y += gpio.c
 smm-y += smihandler.c
 

src/mainboard/lenovo/t430s/Makefile.inc

@@ -14,6 +14,7 @@
 ##
 
 smm-y += smihandler.c
+bootblock-y += variants/$(VARIANT_DIR)/gpio.c
 romstage-y += variants/$(VARIANT_DIR)/gpio.c
 romstage-y += variants/$(VARIANT_DIR)/romstage.c
 ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c

src/mainboard/lenovo/t520/Makefile.inc

@@ -14,6 +14,7 @@
 ##
 
 smm-y += smihandler.c
+bootblock-y += variants/$(VARIANT_DIR)/gpio.c
 romstage-y += variants/$(VARIANT_DIR)/gpio.c
 romstage-y += variants/$(VARIANT_DIR)/romstage.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/lenovo/t530/Makefile.inc

@@ -14,6 +14,7 @@
 ##
 
 smm-y += smihandler.c
+bootblock-y += variants/$(VARIANT_DIR)/gpio.c
 romstage-y += variants/$(VARIANT_DIR)/gpio.c
 romstage-y += variants/$(VARIANT_DIR)/romstage.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/lenovo/x131e/Makefile.inc

@@ -13,6 +13,7 @@
 ## GNU General Public License for more details.
 ##
 
+bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc

@@ -16,6 +16,7 @@
 subdirs-y += spd
 
 smm-y += smihandler.c
+bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/lenovo/x220/Makefile.inc

@@ -14,6 +14,7 @@
 ##
 
 smm-y += smihandler.c
+bootblock-y += variants/$(VARIANT_DIR)/gpio.c
 romstage-y += variants/$(VARIANT_DIR)/gpio.c
 romstage-y += variants/$(VARIANT_DIR)/romstage.c
 

src/mainboard/lenovo/x230/Makefile.inc

@@ -14,6 +14,7 @@
 ##
 
 smm-y += smihandler.c
+bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/msi/ms7707/Makefile.inc

@@ -1 +1,2 @@
+bootblock-y += gpio.c
 romstage-y += gpio.c

src/mainboard/roda/rv11/Makefile.inc

@@ -13,6 +13,7 @@
 ## GNU General Public License for more details.
 ##
 
+bootblock-y += gpio.c
 romstage-y += gpio.c
 
 romstage-y += variants/$(VARIANT_DIR)/romstage.c

src/mainboard/samsung/lumpy/Makefile.inc

@@ -27,6 +27,7 @@ $(SPD_BIN):
 cbfs-files-y += spd.bin
 spd.bin-file := $(SPD_BIN)
 spd.bin-type := spd
+bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/samsung/stumpy/Makefile.inc

@@ -15,6 +15,7 @@
 
 romstage-y += chromeos.c
 ramstage-y += chromeos.c
+bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/sapphire/pureplatinumh61/Makefile.inc

@@ -14,6 +14,7 @@
 # GNU General Public License for more details.
 #
 
+bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/northbridge/intel/sandybridge/Kconfig

@@ -62,10 +62,6 @@ config VGA_BIOS_ID
 	string
 	default "8086,0106"
 
-config BOOTBLOCK_NORTHBRIDGE_INIT
-	string
-	default "northbridge/intel/sandybridge/bootblock.c"
-
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xf0000000

src/northbridge/intel/sandybridge/Makefile.inc

@@ -15,6 +15,8 @@
 
 ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE),y)
 
+bootblock-y += bootblock.c
+
 ramstage-y += memmap.c
 ramstage-y += northbridge.c
 ramstage-y += pcie.c
@@ -44,7 +46,6 @@ mrc.bin-type := mrc
 endif
 romstage-y += romstage.c
 romstage-y += early_init.c
-romstage-y += ../../../arch/x86/walkcbfs.S
 
 smm-y += finalize.c
 

src/northbridge/intel/sandybridge/bootblock.c

@@ -12,11 +12,10 @@
  */
 
 #include <device/pci_ops.h>
+#include <cpu/intel/car/bootblock.h>
+#include "sandybridge.h"
 
-/* Just re-define this instead of including sandybridge.h. It blows up romcc. */
-#define PCIEXBAR	0x60
-
-static void bootblock_northbridge_init(void)
+void bootblock_early_northbridge_init(void)
 {
 	uint32_t reg;
 

src/southbridge/intel/bd82x6x/Kconfig

@@ -57,10 +57,6 @@ config DRAM_RESET_GATE_GPIO
 	int
 	default 60
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "southbridge/intel/bd82x6x/bootblock.c"
-
 config SERIRQ_CONTINUOUS_MODE
 	bool
 	default n

src/southbridge/intel/bd82x6x/Makefile.inc

@@ -15,6 +15,9 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_C216)$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X),y)
 
+bootblock-y += bootblock.c
+bootblock-y += early_pch.c
+
 ramstage-y += pch.c
 ramstage-y += azalia.c
 ramstage-y += lpc.c

src/southbridge/intel/bd82x6x/bootblock.c

@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <cpu/intel/car/bootblock.h>
 #include <device/pci_ops.h>
 #include "pch.h"
 
@@ -32,18 +33,8 @@ static void enable_spi_prefetch(void)
 
 static void enable_port80_on_lpc(void)
 {
-	pci_devfn_t dev = PCH_LPC_DEV;
-
 	/* Enable port 80 POST on LPC */
-	pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
-#if 0
 	RCBA32(GCS) &= (~0x04);
-#else
-	volatile u32 *gcs = (volatile u32 *)(DEFAULT_RCBA + GCS);
-	u32 reg32 = *gcs;
-	reg32 = reg32 & ~0x04;
-	*gcs = reg32;
-#endif
 }
 
 static void set_spi_speed(void)
@@ -66,9 +57,12 @@ static void set_spi_speed(void)
 	RCBA8(0x3893) = ssfc;
 }
 
-static void bootblock_southbridge_init(void)
+void bootblock_early_southbridge_init(void)
 {
 	enable_spi_prefetch();
+
+	early_pch_init();
+
 	enable_port80_on_lpc();
 	set_spi_speed();