diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
index 33898e3280..954b669515 100644
--- a/src/cpu/intel/speedstep/acpi.c
+++ b/src/cpu/intel/speedstep/acpi.c
@@ -25,6 +25,7 @@
 #include <arch/acpigen.h>
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
+#include <cpu/intel/acpi.h>
 #include <device/device.h>
 
 // XXX: PSS table values for power consumption are for Merom only
@@ -83,8 +84,6 @@ void generate_cpu_entries(void)
 
 			int max_states=8;
 			int busratio_step=2;
-#define IA32_PLATFORM_ID 0x017
-#define IA32_PERF_STS 0x198
 			msr = rdmsr(IA32_PERF_STS);
 			int busratio_min=(msr.lo >> 24) & 0x1f;
 			int busratio_max=(msr.hi >> (40-32)) & 0x1f;
diff --git a/src/include/cpu/intel/acpi.h b/src/include/cpu/intel/acpi.h
new file mode 100644
index 0000000000..35a45a0021
--- /dev/null
+++ b/src/include/cpu/intel/acpi.h
@@ -0,0 +1,5 @@
+#define IA32_PLATFORM_ID  0x017
+#define IA32_PERF_STS     0x198
+#define IA32_PERF_CTL     0x199
+#define MSR_THERM2_CTL    0x19D
+#define IA32_MISC_ENABLES 0x1A0
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index 072dad67f8..774f88f60f 100644
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -33,6 +33,7 @@
 
 #include <console/console.h>
 #include <cpu/x86/bist.h>
+#include <cpu/intel/acpi.h>
 
 #include "southbridge/intel/i3100/i3100_early_smbus.c"
 #include "southbridge/intel/i3100/i3100_early_lpc.c"
@@ -44,11 +45,6 @@
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
-#define IA32_PERF_STS     0x198
-#define IA32_PERF_CTL     0x199
-#define MSR_THERM2_CTL    0x19D
-#define IA32_MISC_ENABLES 0x1A0
-
 /* SATA */
 #define SATA_MAP 0x90