soc/intel/apollolake: Disable Monitor and Mwait feature
Monitor/Mwait is broken on APL. So, it needs to be disabled. BUG=chrome-os-partner:56922 BRANCH=None Change-Id: I12cd4280de62e0a639b43538171660ee4c0a0265 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/17200 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
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@ -21,6 +21,9 @@
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#define PM_CAP_TURBO_MODE (1 << 1)
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#define PM_CAP_TURBO_MODE (1 << 1)
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#define MSR_IA32_MISC_ENABLES 0x1a0
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#define MSR_IA32_MISC_ENABLES 0x1a0
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/* Disable the Monitor Mwait FSM feature */
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#define MONITOR_MWAIT_DIS_MASK 0x40000
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#define H_MISC_DISABLE_TURBO (1 << 6)
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#define H_MISC_DISABLE_TURBO (1 << 6)
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enum {
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enum {
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@ -29,6 +29,7 @@
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#include <soc/cpu.h>
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#include <soc/cpu.h>
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#include <soc/iomap.h>
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#include <soc/iomap.h>
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#include <soc/smm.h>
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#include <soc/smm.h>
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#include <cpu/intel/turbo.h>
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static const struct reg_script core_msr_script[] = {
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static const struct reg_script core_msr_script[] = {
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/* Enable C-state and IO/MWAIT redirect */
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/* Enable C-state and IO/MWAIT redirect */
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@ -40,6 +41,8 @@ static const struct reg_script core_msr_script[] = {
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(ACPI_PMIO_CST_REG | (PMG_IO_BASE_CST_RNG_BLK_SIZE << 16))),
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(ACPI_PMIO_CST_REG | (PMG_IO_BASE_CST_RNG_BLK_SIZE << 16))),
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/* Disable C1E */
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/* Disable C1E */
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REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0),
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REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0),
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/* Disable support for MONITOR and MWAIT instructions */
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REG_MSR_RMW(MSR_IA32_MISC_ENABLES, ~MONITOR_MWAIT_DIS_MASK, 0),
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REG_SCRIPT_END
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REG_SCRIPT_END
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};
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};
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