Add support for LiPPERT Hurricane-LX (EPIC board with AMD Geode-LX,
CS5536, ITE IT8712F). Board support is based on the SpaceRunner-LX (with tiny bits from the RoadRunner-LX) even though the hardware really was the ancestor of our three other -LX boards and in fact among the earliest Geode-LX boards on the market. (Might even have been the first Geode-LX EPIC?) Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5801 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Jens Rottmann
Myles Watson
parent
6ea2115cea
commit
36224b479b
|
|
@ -5,6 +5,8 @@ choice
|
|||
|
||||
config BOARD_LIPPERT_FRONTRUNNER
|
||||
bool "Cool Frontrunner"
|
||||
config BOARD_LIPPERT_HURRICANE_LX
|
||||
bool "Hurricane-LX"
|
||||
config BOARD_LIPPERT_LITERUNNER_LX
|
||||
bool "Cool LiteRunner-LX"
|
||||
config BOARD_LIPPERT_ROADRUNNER_LX
|
||||
|
|
@ -15,6 +17,7 @@ config BOARD_LIPPERT_SPACERUNNER_LX
|
|||
endchoice
|
||||
|
||||
source "src/mainboard/lippert/frontrunner/Kconfig"
|
||||
source "src/mainboard/lippert/hurricane-lx/Kconfig"
|
||||
source "src/mainboard/lippert/literunner-lx/Kconfig"
|
||||
source "src/mainboard/lippert/roadrunner-lx/Kconfig"
|
||||
source "src/mainboard/lippert/spacerunner-lx/Kconfig"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,45 @@
|
|||
if BOARD_LIPPERT_HURRICANE_LX
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select ARCH_X86
|
||||
select CPU_AMD_LX
|
||||
select NORTHBRIDGE_AMD_LX
|
||||
select SOUTHBRIDGE_AMD_CS5536
|
||||
select SUPERIO_ITE_IT8712F
|
||||
select HAVE_PIRQ_TABLE
|
||||
select PIRQ_ROUTE
|
||||
select UDELAY_TSC
|
||||
select CACHE_AS_RAM
|
||||
# Board is equipped with a 1 MB SPI flash, however, due to limitations
|
||||
# of the IT8712F Super I/O, only the top 512 KB are directly mapped.
|
||||
select BOARD_ROMSIZE_KB_512
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default lippert/hurricane-lx
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "Hurricane-LX"
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 8
|
||||
|
||||
config BOARD_OLD_REVISION
|
||||
bool "Board is old pre-3.0 revision"
|
||||
default n
|
||||
help
|
||||
Look on the bottom side for a number like 406-0001-30. The last 2
|
||||
digits state the PCB revision (3.0 in this example). For 2.0 or older
|
||||
boards choose Y, for 3.0 and newer say N.
|
||||
|
||||
config ONBOARD_UARTS_RS485
|
||||
bool "Switch on-board serial ports to RS485"
|
||||
default n
|
||||
help
|
||||
If selected, both on-board serial ports will operate in RS485 mode
|
||||
instead of RS232.
|
||||
|
||||
endif # BOARD_LIPPERT_HURRICANE_LX
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 LiPPERT Embedded Computers GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
extern struct chip_operations mainboard_ops;
|
||||
|
||||
struct mainboard_config {};
|
||||
|
|
@ -0,0 +1,90 @@
|
|||
chip northbridge/amd/lx
|
||||
device pci_domain 0 on
|
||||
device pci 1.0 on end # Northbridge
|
||||
device pci 1.1 on end # Graphics
|
||||
device pci 1.2 on end # AES
|
||||
chip southbridge/amd/cs5536
|
||||
# IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK
|
||||
# SIRQ Mode = Active(Quiet) mode. Save power....
|
||||
# Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse,
|
||||
# UARTs, etc IRQs. OK
|
||||
register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010
|
||||
register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above
|
||||
register "lpc_serirq_mode" = "1"
|
||||
register "enable_gpio_int_route" = "0x0D0C0700"
|
||||
register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
|
||||
register "enable_USBP4_device" = "0" # 0:host, 1:device
|
||||
register "enable_USBP4_overcurrent" = "0" # 0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
|
||||
register "com1_enable" = "0"
|
||||
register "com1_address" = "0x3E8"
|
||||
register "com1_irq" = "6"
|
||||
register "com2_enable" = "0"
|
||||
register "com2_address" = "0x2E8"
|
||||
register "com2_irq" = "6"
|
||||
register "unwanted_vpci[0]" = "0" # End of list has a zero
|
||||
device pci 8.0 on end # Slot4
|
||||
device pci 9.0 on end # Slot3
|
||||
device pci a.0 on end # Slot2
|
||||
device pci b.0 on end # Slot1
|
||||
device pci c.0 on end # IT8888
|
||||
device pci d.0 on end # Mini-PCI
|
||||
device pci e.0 on end # Ethernet
|
||||
device pci f.0 on # ISA Bridge
|
||||
chip superio/ite/it8712f
|
||||
device pnp 2e.0 on # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.2 on # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.3 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.4 on # EC
|
||||
io 0x60 = 0x290 # EC
|
||||
io 0x62 = 0x298 # PME
|
||||
irq 0x70 = 9
|
||||
end
|
||||
device pnp 2e.5 on # PS/2 keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 2e.6 on # PS/2 mouse
|
||||
irq 0x70 = 12
|
||||
end
|
||||
device pnp 2e.7 on # GPIO
|
||||
io 0x62 = 0x1220 # Simple I/O
|
||||
io 0x64 = 0x1228 # SPI
|
||||
end
|
||||
device pnp 2e.8 off # MIDI
|
||||
io 0x60 = 0x300
|
||||
irq 0x70 = 9
|
||||
end
|
||||
device pnp 2e.9 off # Game port
|
||||
io 0x60 = 0x220
|
||||
end
|
||||
device pnp 2e.a off end # CIR
|
||||
end
|
||||
end
|
||||
device pci f.2 on end # IDE
|
||||
device pci f.3 on end # Audio
|
||||
device pci f.4 on end # OHCI
|
||||
device pci f.5 on end # EHCI
|
||||
end
|
||||
end
|
||||
# APIC cluster is late CPU init.
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/model_lx
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 LiPPERT Embedded Computers GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* Based on irq_tables.c from the SpaceRunner-LX mainboard. */
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
#include <console/console.h>
|
||||
#include <arch/io.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
#include "../../../southbridge/amd/cs5536/cs5536.h"
|
||||
|
||||
/* Platform IRQs */
|
||||
#define PIRQA 10
|
||||
#define PIRQB 11
|
||||
#define PIRQC 5
|
||||
#define PIRQD 15
|
||||
|
||||
/* Map */
|
||||
#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
|
||||
#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
|
||||
#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
|
||||
#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
|
||||
|
||||
/* Link */
|
||||
#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
|
||||
#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
|
||||
#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
|
||||
#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
|
||||
0x00, /* Where the interrupt router lies (bus) */
|
||||
(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
|
||||
0x00, /* IRQs devoted exclusively to PCI usage */
|
||||
0x100B, /* Vendor */
|
||||
0x002B, /* Device */
|
||||
0, /* Crap (miniport) */
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
|
||||
0x36, /* u8 checksum, this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
{
|
||||
/* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
|
||||
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */
|
||||
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
|
||||
{0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */
|
||||
{0x00, (0x0B << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0}, /* slot1 */
|
||||
{0x00, (0x0A << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x2, 0x0}, /* slot2 */
|
||||
{0x00, (0x09 << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x3, 0x0}, /* slot3 */
|
||||
{0x00, (0x08 << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x4, 0x0}, /* slot4 */
|
||||
{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}}, 0x5, 0x0}, /* Mini-PCI */
|
||||
}
|
||||
};
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr);
|
||||
}
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 LiPPERT Embedded Computers GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* Based on mainboard.c from the SpaceRunner-LX mainboard. */
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdint.h>
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include "chip.h"
|
||||
|
||||
/* Bit1 switches Com1 to RS485, bit2 same for Com2. */
|
||||
#if CONFIG_ONBOARD_UARTS_RS485
|
||||
#define SIO_GP1X_CONFIG 0x06
|
||||
#else
|
||||
#define SIO_GP1X_CONFIG 0x00
|
||||
#endif
|
||||
|
||||
static const u16 ec_init_table[] = { /* hi=data, lo=index */
|
||||
0x1900, /* Enable monitoring */
|
||||
0x0351, /* TMPIN1,2 diode mode, TMPIN3 off */
|
||||
0x805C, /* Unlock zero adjust */
|
||||
0x7056, 0x3C57, /* Zero adjust TMPIN1,2 */
|
||||
0x005C, /* Lock zero adjust */
|
||||
0xD014 /* Also set FAN_CTL polarity to Active High */
|
||||
};
|
||||
|
||||
static void init(struct device *dev)
|
||||
{
|
||||
unsigned int gpio_base, i;
|
||||
printk(BIOS_DEBUG, "LiPPERT Hurricane-LX ENTER %s\n", __func__);
|
||||
|
||||
/* Init CS5536 GPIOs */
|
||||
gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD,
|
||||
PCI_DEVICE_ID_AMD_CS5536_ISA, 0), PCI_BASE_ADDRESS_1) - 1;
|
||||
|
||||
outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD#
|
||||
outl(0x00000040, gpio_base + 0x08); // GPIO6 open drain 1 - LAN_PD# (jumpered GPIO per default)
|
||||
outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD#
|
||||
outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM#
|
||||
outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM#
|
||||
#if !CONFIG_BOARD_OLD_REVISION
|
||||
outl(0x00000800, gpio_base + 0x94); // GPIO27 out aux2 1 - 32kHz
|
||||
outl(0x00000800, gpio_base + 0x84); // GPIO27 output 1 - 32kHz
|
||||
#endif
|
||||
outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - 32kHz (new) / PM-LED (old)
|
||||
|
||||
/* Init Environment Controller. */
|
||||
for (i = 0; i < ARRAY_SIZE(ec_init_table); i++) {
|
||||
u16 val = ec_init_table[i];
|
||||
outb((u8)val, 0x0295);
|
||||
outb(val >> 8, 0x0296);
|
||||
}
|
||||
|
||||
/* bit2 = RS485_EN2, bit1 = RS485_EN1 */
|
||||
outb(SIO_GP1X_CONFIG, 0x1220); /* Simple-I/O GP17-10 */
|
||||
|
||||
printk(BIOS_DEBUG, "LiPPERT Hurricane-LX EXIT %s\n", __func__);
|
||||
}
|
||||
|
||||
static void enable_dev(struct device *dev)
|
||||
{
|
||||
dev->ops->init = init;
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
CHIP_NAME("LiPPERT Hurricane-LX Mainboard")
|
||||
.enable_dev = enable_dev,
|
||||
};
|
||||
|
|
@ -0,0 +1,175 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2010 LiPPERT Embedded Computers GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* Based on romstage.c from the SpaceRunner-LX mainboard. */
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <arch/hlt.h>
|
||||
#include <console/console.h>
|
||||
#include "lib/ramtest.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
#include "cpu/x86/msr.h"
|
||||
#include <cpu/amd/lxdef.h>
|
||||
#include <cpu/amd/geode_post_code.h>
|
||||
#include "southbridge/amd/cs5536/cs5536.h"
|
||||
|
||||
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
|
||||
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
|
||||
#include "superio/ite/it8712f/it8712f_early_serial.c"
|
||||
|
||||
/* Bit0 enables Spread Spectrum. */
|
||||
#define SMC_CONFIG 0x01
|
||||
|
||||
#define ManualConf 1 /* No automatic strapped PLL config */
|
||||
#define PLLMSRhi 0x0000049C /* Manual settings for the PLL */
|
||||
#define PLLMSRlo 0x00DE6001
|
||||
#define DIMM0 0xA0
|
||||
#define DIMM1 0xA2
|
||||
|
||||
static inline int spd_read_byte(unsigned int device, unsigned int address)
|
||||
{
|
||||
if (device != DIMM0)
|
||||
return 0xFF; /* No DIMM1, don't even try. */
|
||||
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#if !CONFIG_BOARD_OLD_REVISION
|
||||
/* Send config data to System Management Controller via SMB. */
|
||||
static int smc_send_config(unsigned char config_data)
|
||||
{
|
||||
if (smbus_check_stop_condition(SMBUS_IO_BASE))
|
||||
return 1;
|
||||
if (smbus_start_condition(SMBUS_IO_BASE))
|
||||
return 2;
|
||||
if (smbus_send_slave_address(SMBUS_IO_BASE, 0x50)) // SMC address
|
||||
return 3;
|
||||
if (smbus_send_command(SMBUS_IO_BASE, 0x28)) // set config data
|
||||
return 4;
|
||||
if (smbus_send_command(SMBUS_IO_BASE, 0x01)) // data length
|
||||
return 5;
|
||||
if (smbus_send_command(SMBUS_IO_BASE, config_data))
|
||||
return 6;
|
||||
smbus_stop_condition(SMBUS_IO_BASE);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#include "northbridge/amd/lx/raminit.h"
|
||||
#include "northbridge/amd/lx/pll_reset.c"
|
||||
#include "northbridge/amd/lx/raminit.c"
|
||||
#include "lib/generic_sdram.c"
|
||||
#include "cpu/amd/model_lx/cpureginit.c"
|
||||
#include "cpu/amd/model_lx/syspreinit.c"
|
||||
#include "cpu/amd/model_lx/msrinit.c"
|
||||
|
||||
static const u16 sio_init_table[] = { // hi=data, lo=index
|
||||
0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...)
|
||||
0x042C, // disable ATXPG; VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 enabled
|
||||
0x1423, // don't delay PoWeROK1/2
|
||||
0x9072, // watchdog triggers PWROK, counts seconds
|
||||
#if !CONFIG_USE_WATCHDOG_ON_BOOT
|
||||
0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0
|
||||
#endif
|
||||
0xBF25, 0x172A, 0xF326, // select GPIO function for most pins
|
||||
0xBF27, 0xFF28, 0x2D29, // (GP36=FAN_CTL3 (PWM), GP23,22,16,15=SPI, GP13=PWROK1)
|
||||
0x66B8, 0x0CB9, // enable pullups on SPI, RS485_EN
|
||||
0x07C0, // enable Simple-I/O for GP12-10= RS485_EN2,1, WD_ACTIVE
|
||||
0x06C8, // config GP12,11 as output, GP10 as input
|
||||
0x2DF5, // map Hw Monitor Thermal Output to GP55
|
||||
#if CONFIG_BOARD_OLD_REVISION
|
||||
0x1F2A, 0xC072, // switch GP13 to GPIO, WDT output from PWROK to KRST
|
||||
#endif
|
||||
};
|
||||
|
||||
/* Early mainboard specific GPIO setup. */
|
||||
static void mb_gpio_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */
|
||||
it8712f_enter_conf();
|
||||
for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) {
|
||||
u16 val = sio_init_table[i];
|
||||
outb((u8)val, SIO_INDEX);
|
||||
outb(val >> 8, SIO_DATA);
|
||||
}
|
||||
it8712f_exit_conf();
|
||||
}
|
||||
|
||||
void main(unsigned long bist)
|
||||
{
|
||||
post_code(0x01);
|
||||
|
||||
static const struct mem_controller memctrl[] = {
|
||||
{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
|
||||
};
|
||||
|
||||
SystemPreInit();
|
||||
msr_init();
|
||||
|
||||
cs5536_early_setup();
|
||||
|
||||
/*
|
||||
* Note: Must do this AFTER the early_setup! It is counting on some
|
||||
* early MSR setup for CS5536.
|
||||
*/
|
||||
it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter
|
||||
mb_gpio_init();
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
pll_reset(ManualConf);
|
||||
|
||||
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
|
||||
|
||||
#if CONFIG_BOARD_OLD_REVISION
|
||||
/*
|
||||
* Old revision boards need a jumper shorting the power button to power
|
||||
* on automatically. So we must disable the button's fail-safe function,
|
||||
* or the board will shut down after 4 s.
|
||||
*/
|
||||
outl(0, PMS_IO_BASE + PM_FSD); // Fail-Save Delay register
|
||||
#else
|
||||
int err;
|
||||
/* bit0 = Spread Spectrum */
|
||||
if ((err = smc_send_config(SMC_CONFIG))) {
|
||||
print_err("ERROR ");
|
||||
print_err_char('0'+err);
|
||||
print_err(" sending config data to SMC\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
sdram_initialize(1, memctrl);
|
||||
|
||||
/* Check memory. */
|
||||
/* ram_check(0, 640 * 1024); */
|
||||
|
||||
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
|
||||
return;
|
||||
}
|
||||
Loading…
Reference in New Issue