soc/intel/xeon_sp/cpx: Modify PCH_IOAPIC_BUS_NUMBER

The PCH IOAPIC is not PCI discoverable.
Linux checks the BDF set in DMAR against the PCI class if it is a PIC,
which 00:1F.0 for instance isn't.

The SINIT ACM on the other hand bails out with ERROR CLASS:0xA, MAJOR
3, MINOR 7 if the BUS number is 0.

Change-Id: I9b8d35a66762247fde698e459e30ce4c8a2c7eb0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>

src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h

@@ -112,7 +112,7 @@
 #define HPET_DEV_NUM            PCH_DEV_SLOT_LPC
 #define HPET0_FUNC_NUM          0x00
 
-#define PCH_IOAPIC_BUS_NUMBER   0x00
+#define PCH_IOAPIC_BUS_NUMBER   0xF0
 #define PCH_IOAPIC_DEV_NUM      0x1F
 #define PCH_IOAPIC_FUNC_NUM     0x00