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ipq806x: modify imem layout 

With introduction of uber-sbl SRAM usage pattern is changing, this
introduces the new memory layout.

This patch overlays DDR initialization code with uber-sbl, as uber-sbl
goes out of scope as soon as bootblock starts.

A 4K block at offset 0x3f000 added in the comments, this is a shared
structure used by different QCA modules.

This suggested layout is not final, but will allow to move closer to
the production image.

BRANCH=storm
BUG=chrome-os-partner:34161
TEST=with other patches applied Storm boots all the way to rombase and
     initializes DRAM.

Change-Id: I46af81b39b09935aa7fffdabda223e7e64c7a446
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a20c0570361038c0ae406dcb1f4bc657eea120f6
Original-Change-Id: I927f6ffc524fc8f0effd7b91d3f5d1e8d6be1530
Original-Signed-off-by: Deepa Dinamani <deepad@codeaurora.org>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/229023
Reviewed-on: http://review.coreboot.org/9683
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Deepa Dinamani 2014-10-27 15:40:05 -07:00 committed by Patrick Georgi
parent 55e2f393a7
commit 36417aa742
1 changed files with 19 additions and 10 deletions
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29
src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
View File

@ -18,23 +18,32 @@
*/ */
#include <memlayout.h> #include <memlayout.h>
#include <vendorcode/google/chromeos/vboot2/memlayout.h>
#include <arch/header.ld> #include <arch/header.ld>
/* TODO: This should be revised by someone who understands the SoC better. */
SECTIONS SECTIONS
{ {
/* TODO: add SRAM_START(), SRAM_END() and REGION(reserved_sbl) */ SRAM_START(0x2A000000)
TTB(0x2A05C000, 48K) /* This includes bootblock image, can be reused after bootblock starts */
/* UBER_SBL(0x2A000000, 48K) */
/* DDR(0x2A000000, 48K) */
BOOTBLOCK(0x2A00C000, 24K)
OVERLAP_VERSTAGE_ROMSTAGE(0x2A012000, 64K)
VBOOT2_WORK(0x2A022000, 16K)
PRERAM_CBMEM_CONSOLE(0x2A026000, 32K)
/* 0x2e000..0x3F000 68 KB free */
/* Keep the below area reserved at all times, it is used by various QCA
components as shared data
QCA_SHARED_RAM(2A03F000, 4K)
*/
STACK(0x2A040000, 16K)
CBFS_CACHE(0x2A044000, 96K)
TTB(0x2A05C000, 16K)
SRAM_END(0x2A060000)
DRAM_START(0x40000000) DRAM_START(0x40000000)
CBFS_CACHE(0x405C0000, 240K)
STACK(0x405FC000, 16K)
/* TODO: "256K bytes left for TZBSP"... what does that mean? */
BOOTBLOCK(0x40600000, 32K)
PRERAM_CBMEM_CONSOLE(0x40618000, 8K)
ROMSTAGE(0x40620000, 128K)
RAMSTAGE(0x40640000, 128K) RAMSTAGE(0x40640000, 128K)
DMA_COHERENT(0x5A000000, 2M) DMA_COHERENT(0x5A000000, 2M)
} }