mainboard/asus/p8x7x-series: Add new variant P8Z77-M
Constructed out of a mix of autoport results, p8z77-m_pro, and tool dumps. Working: - Core i7-3770K CPU - SeaBIOS 1.13.0 boot to Linux 5.4.24 and Windows 10 1903 (all further tests are under these versions) - USB2 / USB3 - SATA - Gigabit ethernet - CPU temp sensors (memtest86+ 5.0.1) - Hardware monitoring under Linux - Native and MRC raminit - PCIe GPU in both "PCIEX16" slots (16x/4x, nVidia Quadro 600) - Integrated graphics with Intel OpROM and libgfxinit (all ports) - Serial port - Windows with libgfxinit framebuffer - 2ch sound playback, Linux and Windows Not working: - PS/2 mouse - 6ch analog audio out - PCI POST card in PCI slot Untested: - PS/2 keyboard - Internal USB3 ports - Digital audio out Change-Id: If756e791ddce747cb1706414be8e41e83f88922b Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Keith Hui
Angel Pons
parent
f4bb77bd9e
commit
36425312ee
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@ -24,6 +24,7 @@ config VARIANT_DIR
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default "p8z77-m_pro" if BOARD_ASUS_P8Z77_M_PRO
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default "p8z77-v_lx2" if BOARD_ASUS_P8Z77_V_LX2
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default "p8z77-v" if BOARD_ASUS_P8Z77_V
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default "p8z77-m" if BOARD_ASUS_P8Z77_M
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config MAINBOARD_PART_NUMBER
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default "P8C WS" if BOARD_ASUS_P8C_WS
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@ -31,6 +32,7 @@ config MAINBOARD_PART_NUMBER
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default "P8Z77-M PRO" if BOARD_ASUS_P8Z77_M_PRO
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default "P8Z77-V LX2" if BOARD_ASUS_P8Z77_V_LX2
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default "P8Z77-V" if BOARD_ASUS_P8Z77_V
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default "P8Z77-M" if BOARD_ASUS_P8Z77_M
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config OVERRIDE_DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
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@ -38,3 +38,9 @@ config BOARD_ASUS_P8Z77_V
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select MAINBOARD_USES_IFD_GBE_REGION
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select SUPERIO_NUVOTON_NCT6779D
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select USE_NATIVE_RAMINIT
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config BOARD_ASUS_P8Z77_M
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bool "P8Z77-M"
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select BOARD_ASUS_P8X7X_SERIES
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select BOARD_ROMSIZE_KB_8192
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select SUPERIO_NUVOTON_NCT6779D
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@ -0,0 +1,7 @@
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Category: desktop
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Board URL: https://www.asus.com/Motherboards/P8Z77M/
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ROM package: DIP-8
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ROM protocol: SPI
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ROM socketed: y
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Flashrom support: y
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Release year: 2012
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@ -0,0 +1,11 @@
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## SPDX-License-Identifier: GPL-2.0-only
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boot_option=Fallback
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debug_level=Debug
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gfx_uma_size=224M
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nmi=Disable
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sata_mode=AHCI
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#usb3_xxxx options are only used with MRC blob, ignored otherwise
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usb3_mode=Enable
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usb3_drv=Enable
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usb3_streams=Enable
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@ -0,0 +1,136 @@
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## SPDX-License-Identifier: GPL-2.0-only
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# -----------------------------------------------------------------
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entries
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 3 boot_option
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388 4 h 0 reboot_counter
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# -----------------------------------------------------------------
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# coreboot config options: console
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395 4 e 4 debug_level
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# -----------------------------------------------------------------
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# coreboot config options: southbridge
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# Non Maskable Interrupt(NMI) support, which is an interrupt that may
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# occur on a RAM or unrecoverable error.
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408 1 e 1 nmi
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409 2 e 5 power_on_after_fail
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411 2 e 6 sata_mode
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# -----------------------------------------------------------------
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# coreboot config options: northbridge
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# gfx_uma_size
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# Quantity of shared video memory the IGP can use
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#
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416 5 e 7 gfx_uma_size
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# -----------------------------------------------------------------
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# coreboot config options: usb3
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# usb3_mode
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# Controls how the motherboard's USB3 ports act at boot time
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421 2 e 8 usb3_mode
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# usb3_drv
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# Load (or not) pre-OS xHCI USB3 bios driver
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#
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423 1 e 1 usb3_drv
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# usb3_streams
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# Streams can provide more speed (as they can use 64Kb packets),
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# but they might cause incompatibilities with some devices.
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#
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424 1 e 1 usb3_streams
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# -----------------------------------------------------------------
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# Sandy/Ivy Bridge MRC Scrambler Seed values
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# note: MUST NOT be covered by checksum!
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464 32 r 0 mrc_scrambler_seed
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496 32 r 0 mrc_scrambler_seed_s3
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528 16 r 0 mrc_scrambler_seed_chk
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# -----------------------------------------------------------------
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# coreboot config options: check sums
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544 16 h 0 check_sum
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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# Generic on/off enum
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1 0 Disable
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1 1 Enable
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# boot_option
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3 0 Fallback
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3 1 Normal
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# debug_level
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4 0 Emergency
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4 1 Alert
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4 2 Critical
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4 3 Error
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4 4 Warning
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4 5 Notice
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4 6 Info
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4 7 Debug
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4 8 Spew
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# power_on_after_fail
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5 0 Disable
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5 1 Enable
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5 2 Keep
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# sata_mode
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6 0 AHCI
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6 1 Compatible
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6 2 Legacy
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# gfx_uma_size (Intel IGP Video RAM size)
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7 0 32M
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7 1 64M
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7 2 96M
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7 3 128M
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7 4 160M
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7 5 192M
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7 6 224M
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7 7 256M
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7 8 288M
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7 9 320M
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7 10 352M
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7 11 384M
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7 12 416M
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7 13 448M
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7 14 480M
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7 15 512M
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7 16 1024M
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# usb3_mode
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# Disable = Use the port always as USB 2.0 for compatibility
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# Enable = Use the port always as USB 3.0 for speed
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# Auto = Initialize the port as USB 2.0, until the OS loads
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# xHCI USB 3.0 driver
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# SmartAuto = Same as Auto but, if the OS loads the xHCI USB 3.0 driver
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# and the computer is reset, keep the USB 3.0 mode.
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#
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8 0 Disable
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8 1 Enable
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8 2 Auto
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8 3 SmartAuto
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# -----------------------------------------------------------------
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# <startBit[must be byte-aligned]> <endBit[must be byte aligned]>
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# <bit where to start storing checksum[must be 16bits-aligned]>
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checksums
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checksum 392 431 544
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Binary file not shown.
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@ -0,0 +1,107 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <bootblock_common.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <northbridge/intel/sandybridge/pei_data.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <superio/nuvoton/common/nuvoton.h>
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#include <superio/nuvoton/nct6779d/nct6779d.h>
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#include <option.h>
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#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
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const struct southbridge_usb_port mainboard_usb_ports[] = {
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/* {enable, current, oc_pin} */
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{1, 2, 0}, /* Port 0: USB3 front internal header, top */
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{1, 2, 0}, /* Port 1: USB3 front internal header, bottom */
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{1, 2, 1}, /* Port 2: USB3 rear, top */
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{1, 2, 1}, /* Port 3: USB3 rear, bottom */
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{1, 2, 2}, /* Port 4: USB2 rear, PS2 top */
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{1, 2, 2}, /* Port 5: USB2 rear, PS2 bottom */
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{1, 2, 3}, /* Port 6: USB2 rear, ETH, top */
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{1, 2, 3}, /* Port 7: USB2 rear, ETH, bottom */
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{1, 2, 4}, /* Port 8: USB2 internal header USB910, top */
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{1, 2, 4}, /* Port 9: USB2 internal header USB910, bottom */
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{1, 2, 6}, /* Port 10: USB2 internal header USB1112, top */
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{1, 2, 5}, /* Port 11: USB2 internal header USB1112, bottom */
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{1, 2, 5}, /* Port 12: USB2 internal header USB1314, top */
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{1, 2, 6} /* Port 13: USB2 internal header USB1314, bottom */
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};
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void bootblock_mainboard_early_init(void)
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{
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nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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/*
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* TODO: Put PCIe root port 7 (00:1c.6) into subtractive decode and have it accept I/O
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* cycles. This should allow a POST card in the PCI slot, connected via an ASM1083
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* bridge to this port, to receive POST codes.
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*/
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}
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void mainboard_get_spd(spd_raw_data *spd, bool id_only)
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{
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read_spd(&spd[0], 0x50, id_only);
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read_spd(&spd[1], 0x51, id_only);
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read_spd(&spd[2], 0x52, id_only);
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read_spd(&spd[3], 0x53, id_only);
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}
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int mainboard_should_reset_usb(int s3resume)
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{
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return !s3resume;
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}
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void mainboard_fill_pei_data(struct pei_data *pei)
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{
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uint8_t spdaddr[] = {0xa0, 0xa2, 0xa4, 0xa6}; /* SMBus mul 2 */
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uint16_t usbcfg[16][3] = {
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/* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */
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{1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080},
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{1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080},
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{1, 6, 0x0080}, {1, 5, 0x0080}, {1, 5, 0x0080}, {1, 6, 0x0080}
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};
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memcpy(pei->spd_addresses, &spdaddr, sizeof(spdaddr));
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pei->gbe_enable = 0; /* Board uses no Intel GbE but a RTL8111F */
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pei->max_ddr3_freq = 1600; /* 1333=Sandy; 1600=Ivy */
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memcpy(pei->usb_port_config, &usbcfg, sizeof(usbcfg));
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/* ASUS P8Z77-M manual lists some supported DIMMs down to 1.25v */
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pei->ddr3lv_support = 1;
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/*
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* PCIe 3.0 support. As we use Ivy Bridge, let's enable it,
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* but might cause some system instability!
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*/
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pei->pcie_init = 1;
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/*
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* 4 bit switch mask. 0=not switchable, 1=switchable
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* Means once it's loaded the OS, it can swap ports
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* from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf
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*/
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pei->usb3.hs_port_switch_mask = 0xf;
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/*
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* USB 3 mode settings.
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* These are obtained from option table then bit masked to keep within range.
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*/
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/*
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* 0 = Disable: work always as USB 2.0(ehci)
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* 1 = Enable: work always as USB 3.0(xhci)
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* 2 = Auto: work as USB2.0(ehci) until OS loads USB3 xhci driver
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* 3 = Smart Auto : same than Auto, but if OS loads USB3 driver
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* and reboots, it will keep the USB3.0 speed
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*/
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pei->usb3.mode = get_uint_option("usb3_mode", 1) & 0x3;
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/* 1=Load xHCI pre-OS drv */
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pei->usb3.preboot_support = get_uint_option("usb3_drv", 1) & 0x1;
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/*
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* 0=Don't use xHCI streams for better compatibility
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* 1=use xHCI streams for better speed
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*/
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pei->usb3.xhci_streams = get_uint_option("usb3_streams", 1) & 0x1;
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}
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@ -0,0 +1,17 @@
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-- SPDX-License-Identifier: GPL-2.0-or-later
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with HW.GFX.GMA;
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with HW.GFX.GMA.Display_Probing;
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use HW.GFX.GMA;
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use HW.GFX.GMA.Display_Probing;
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private package GMA.Mainboard is
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ports : constant Port_List :=
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(HDMI1, -- DVI-D port
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HDMI3, -- HDMI port
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Analog, -- VGA port
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others => Disabled);
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end GMA.Mainboard;
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@ -0,0 +1,182 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <southbridge/intel/common/gpio.h>
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static const struct pch_gpio_set1 pch_gpio_set1_mode = {
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.gpio0 = GPIO_MODE_GPIO,
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.gpio1 = GPIO_MODE_GPIO,
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.gpio2 = GPIO_MODE_NATIVE,
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.gpio3 = GPIO_MODE_NATIVE,
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.gpio4 = GPIO_MODE_NATIVE,
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.gpio5 = GPIO_MODE_NATIVE,
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.gpio6 = GPIO_MODE_GPIO,
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.gpio7 = GPIO_MODE_GPIO,
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.gpio8 = GPIO_MODE_GPIO,
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.gpio9 = GPIO_MODE_NATIVE,
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.gpio10 = GPIO_MODE_NATIVE,
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.gpio11 = GPIO_MODE_NATIVE,
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.gpio12 = GPIO_MODE_GPIO,
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.gpio13 = GPIO_MODE_GPIO,
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.gpio14 = GPIO_MODE_NATIVE,
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.gpio15 = GPIO_MODE_GPIO,
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.gpio16 = GPIO_MODE_GPIO,
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.gpio17 = GPIO_MODE_GPIO,
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.gpio18 = GPIO_MODE_NATIVE,
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.gpio19 = GPIO_MODE_NATIVE,
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.gpio20 = GPIO_MODE_NATIVE,
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.gpio21 = GPIO_MODE_GPIO,
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.gpio22 = GPIO_MODE_NATIVE,
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.gpio23 = GPIO_MODE_NATIVE,
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.gpio24 = GPIO_MODE_GPIO,
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.gpio25 = GPIO_MODE_NATIVE,
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.gpio26 = GPIO_MODE_NATIVE,
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.gpio27 = GPIO_MODE_GPIO,
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.gpio28 = GPIO_MODE_GPIO,
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.gpio29 = GPIO_MODE_GPIO,
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.gpio30 = GPIO_MODE_NATIVE,
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.gpio31 = GPIO_MODE_GPIO,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_direction = {
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.gpio0 = GPIO_DIR_INPUT,
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.gpio1 = GPIO_DIR_INPUT,
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.gpio6 = GPIO_DIR_INPUT,
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.gpio7 = GPIO_DIR_INPUT,
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.gpio8 = GPIO_DIR_OUTPUT,
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.gpio12 = GPIO_DIR_OUTPUT,
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.gpio13 = GPIO_DIR_INPUT,
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.gpio15 = GPIO_DIR_OUTPUT,
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.gpio16 = GPIO_DIR_INPUT,
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.gpio17 = GPIO_DIR_INPUT,
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.gpio21 = GPIO_DIR_INPUT,
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.gpio24 = GPIO_DIR_OUTPUT,
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.gpio27 = GPIO_DIR_INPUT,
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.gpio28 = GPIO_DIR_OUTPUT,
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.gpio29 = GPIO_DIR_OUTPUT,
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.gpio31 = GPIO_DIR_OUTPUT,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_level = {
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.gpio8 = GPIO_LEVEL_HIGH,
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.gpio12 = GPIO_LEVEL_LOW,
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.gpio15 = GPIO_LEVEL_LOW,
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.gpio24 = GPIO_LEVEL_LOW,
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.gpio28 = GPIO_LEVEL_LOW,
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.gpio29 = GPIO_LEVEL_HIGH,
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.gpio31 = GPIO_LEVEL_HIGH,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_reset = {
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};
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static const struct pch_gpio_set1 pch_gpio_set1_invert = {
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.gpio1 = GPIO_INVERT,
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.gpio13 = GPIO_INVERT,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_blink = {
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};
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static const struct pch_gpio_set2 pch_gpio_set2_mode = {
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.gpio32 = GPIO_MODE_GPIO,
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.gpio33 = GPIO_MODE_GPIO,
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.gpio34 = GPIO_MODE_GPIO,
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.gpio35 = GPIO_MODE_NATIVE,
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.gpio36 = GPIO_MODE_NATIVE,
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.gpio37 = GPIO_MODE_NATIVE,
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.gpio38 = GPIO_MODE_NATIVE,
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.gpio39 = GPIO_MODE_NATIVE,
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.gpio40 = GPIO_MODE_NATIVE,
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.gpio41 = GPIO_MODE_NATIVE,
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.gpio42 = GPIO_MODE_NATIVE,
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.gpio43 = GPIO_MODE_NATIVE,
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.gpio44 = GPIO_MODE_NATIVE,
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.gpio45 = GPIO_MODE_GPIO,
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.gpio46 = GPIO_MODE_GPIO,
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.gpio47 = GPIO_MODE_NATIVE,
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.gpio48 = GPIO_MODE_NATIVE,
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.gpio49 = GPIO_MODE_GPIO,
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.gpio50 = GPIO_MODE_NATIVE,
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.gpio51 = GPIO_MODE_NATIVE,
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.gpio52 = GPIO_MODE_NATIVE,
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.gpio53 = GPIO_MODE_NATIVE,
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.gpio54 = GPIO_MODE_NATIVE,
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.gpio55 = GPIO_MODE_NATIVE,
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.gpio56 = GPIO_MODE_NATIVE,
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.gpio57 = GPIO_MODE_GPIO,
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.gpio58 = GPIO_MODE_NATIVE,
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.gpio59 = GPIO_MODE_NATIVE,
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.gpio60 = GPIO_MODE_NATIVE,
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.gpio61 = GPIO_MODE_NATIVE,
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.gpio62 = GPIO_MODE_NATIVE,
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.gpio63 = GPIO_MODE_NATIVE,
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};
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static const struct pch_gpio_set2 pch_gpio_set2_direction = {
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.gpio32 = GPIO_DIR_OUTPUT,
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.gpio33 = GPIO_DIR_OUTPUT,
|
||||
.gpio34 = GPIO_DIR_INPUT,
|
||||
.gpio45 = GPIO_DIR_INPUT,
|
||||
.gpio46 = GPIO_DIR_INPUT,
|
||||
.gpio49 = GPIO_DIR_INPUT,
|
||||
.gpio57 = GPIO_DIR_OUTPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
.gpio32 = GPIO_LEVEL_HIGH,
|
||||
.gpio33 = GPIO_LEVEL_HIGH,
|
||||
.gpio57 = GPIO_LEVEL_LOW,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_reset = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
.gpio64 = GPIO_MODE_NATIVE,
|
||||
.gpio65 = GPIO_MODE_NATIVE,
|
||||
.gpio66 = GPIO_MODE_NATIVE,
|
||||
.gpio67 = GPIO_MODE_NATIVE,
|
||||
.gpio68 = GPIO_MODE_GPIO,
|
||||
.gpio69 = GPIO_MODE_GPIO,
|
||||
.gpio70 = GPIO_MODE_NATIVE,
|
||||
.gpio71 = GPIO_MODE_NATIVE,
|
||||
.gpio72 = GPIO_MODE_GPIO,
|
||||
.gpio73 = GPIO_MODE_NATIVE,
|
||||
.gpio74 = GPIO_MODE_NATIVE,
|
||||
.gpio75 = GPIO_MODE_NATIVE,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
.gpio68 = GPIO_DIR_INPUT,
|
||||
.gpio69 = GPIO_DIR_INPUT,
|
||||
.gpio72 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
||||
};
|
||||
|
||||
const struct pch_gpio_map mainboard_gpio_map = {
|
||||
.set1 = {
|
||||
.mode = &pch_gpio_set1_mode,
|
||||
.direction = &pch_gpio_set1_direction,
|
||||
.level = &pch_gpio_set1_level,
|
||||
.blink = &pch_gpio_set1_blink,
|
||||
.invert = &pch_gpio_set1_invert,
|
||||
.reset = &pch_gpio_set1_reset,
|
||||
},
|
||||
.set2 = {
|
||||
.mode = &pch_gpio_set2_mode,
|
||||
.direction = &pch_gpio_set2_direction,
|
||||
.level = &pch_gpio_set2_level,
|
||||
.reset = &pch_gpio_set2_reset,
|
||||
},
|
||||
.set3 = {
|
||||
.mode = &pch_gpio_set3_mode,
|
||||
.direction = &pch_gpio_set3_direction,
|
||||
.level = &pch_gpio_set3_level,
|
||||
.reset = &pch_gpio_set3_reset,
|
||||
},
|
||||
};
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
0x10ec0887, /* Codec Vendor / Device ID: Realtek */
|
||||
0x104384a8, /* Subsystem ID */
|
||||
15, /* Number of 4 dword sets */
|
||||
AZALIA_SUBVENDOR(0, 0x104384a8),
|
||||
AZALIA_PIN_CFG(0, 0x11, 0x90430130),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x01014410),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x01a19c50),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x02a19c60),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x0181345f),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
|
||||
AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x4016c629),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x01446140),
|
||||
AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
|
||||
|
||||
0x80862806, /* Codec Vendor / Device ID: Intel */
|
||||
0x80860101, /* Subsystem ID */
|
||||
4, /* Number of 4 dword sets */
|
||||
AZALIA_SUBVENDOR(3, 0x80860101),
|
||||
AZALIA_PIN_CFG(3, 0x05, 0x58560010),
|
||||
AZALIA_PIN_CFG(3, 0x06, 0x58560020),
|
||||
AZALIA_PIN_CFG(3, 0x07, 0x18560030),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[0] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip northbridge/intel/sandybridge
|
||||
device domain 0 on
|
||||
subsystemid 0x1043 0x84ca inherit
|
||||
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
|
||||
register "gen1_dec" = "0x000c0291"
|
||||
|
||||
device pci 1c.0 on end # PCIe Port #1 (PCIe x4 slot)
|
||||
device pci 1c.1 off end # PCIe Port #2
|
||||
device pci 1c.2 off end # PCIe Port #3
|
||||
device pci 1c.3 off end # PCIe Port #4
|
||||
device pci 1c.4 on end # PCIe Port #5 (PCIe x1 slot)
|
||||
device pci 1c.5 on end # PCIe Port #6
|
||||
device pci 1c.6 on end # PCIe Port #7 (PCI slot via ASM1083)
|
||||
device pci 1c.7 off end # PCIe Port #8
|
||||
device pci 1f.0 on # LPC bridge
|
||||
chip superio/nuvoton/nct6779d
|
||||
device pnp 2e.1 off end # Parallel
|
||||
device pnp 2e.2 on # UART A
|
||||
io 0x60 = 0x3f8 # COM1 address
|
||||
irq 0x70 = 4
|
||||
# Below are global config settings to replicate OEM
|
||||
drq 0x26 = 0x10 # Before accessing CR10/11/13/14, CR26:4 must be set to 1
|
||||
drq 0x13 = 0xff # IRQs 0-15 active low
|
||||
drq 0x14 = 0xff
|
||||
drq 0x1a = 0x02
|
||||
drq 0x1b = 0x60
|
||||
drq 0x2c = 0x00 # GP27, 3VSBSW#, No TSI
|
||||
end
|
||||
device pnp 2e.3 off end # UART B, IR
|
||||
device pnp 2e.5 on # PS2 KBC
|
||||
io 0x60 = 0x0060 # KBC1 base
|
||||
io 0x62 = 0x0064 # KBC2 base
|
||||
irq 0x70 = 1 # Keyboard IRQ
|
||||
irq 0x72 = 12 # Mouse IRQ
|
||||
drq 0xf0 = 0x82 # KBC 12Mhz/A20 speed/sw KBRST
|
||||
drq 0x2a = 0x48 # UART A, PS/2 mouse, PS/2 keyboard
|
||||
drq 0x22 = 0xd7 # Power down UART B and LPT
|
||||
end
|
||||
device pnp 2e.6 off end # CIR
|
||||
device pnp 2e.8 on # WDT1
|
||||
drq 0xe0 = 0x7f # GP07 output
|
||||
drq 0xe1 = 0x80 # GP07 high
|
||||
end
|
||||
device pnp 2e.a on # ACPI
|
||||
drq 0xe7 = 0x11 # HWM reset by LRESET#, 0.5s S3 delay for compatibility
|
||||
drq 0xf2 = 0x5d # Enable RSTOUT[0-2]# and PME
|
||||
end
|
||||
device pnp 2e.b on # HWM, front panel LED
|
||||
io 0x60 = 0x290 # HWM address
|
||||
io 0x62 = 0 # SB-TSI address (not used)
|
||||
drq 0xe4 = 0xf9 # GP50, GP52, PWROK#
|
||||
drq 0xf0 = 0x3e # Enable all fan input debouncers
|
||||
end
|
||||
device pnp 2e.e off end # CIR wake-up
|
||||
device pnp 2e.f on # GPIO PP/OD select
|
||||
drq 0xe4 = 0xfc # GP50,GP51 PP
|
||||
drq 0xe6 = 0x7f # GP7x OD
|
||||
end
|
||||
device pnp 2e.9 off end # GPIO 8
|
||||
device pnp 2e.308 on end # GPIO by I/O
|
||||
device pnp 2e.108 on end # GPIO 0
|
||||
device pnp 2e.109 on end # GPIO 1
|
||||
device pnp 2e.209 on # GPIO 2
|
||||
drq 0xe0 = 0xbf # GP26 output
|
||||
drq 0xe1 = 0xc0 # GP26 high
|
||||
end
|
||||
device pnp 2e.309 off end # GPIO 3
|
||||
device pnp 2e.409 off end # GPIO 4
|
||||
device pnp 2e.509 on # GPIO 5
|
||||
drq 0xf4 = 0xfc # GP50,GP51 output
|
||||
drq 0xf5 = 0xc4 # GP50,GP51 low
|
||||
end
|
||||
device pnp 2e.609 off end # GPIO 6
|
||||
device pnp 2e.709 off end # GPIO 7
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
Loading…
Reference in New Issue