mb/system76/whl-u: Add System76 Galago Pro 3 Rev C
Tested with TianoCore payload (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - NVMe port - SATA port - SD card slot - Left USB 3 Type-A port - Right USB 3 Type-A port - Right USB 3 Type-C port - Webcam - Ethernet - Integrated graphics using Intel GOP driver - mDP output - HDMI output - Internal microphone - Internal speakers - 3.5mm audio input - 3.5mm audio output - S3 suspend/resume - Flashing with flashrom - Booting to Ubuntu Linux 20.10 and Windows 10 Not tested: - Thunderbolt functionality Change-Id: I5c992e603dbd57ae1b4ddc3a0f9bfc92d6acc813 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Crawford
Patrick Georgi
parent
c0538d4613
commit
3647e86862
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if BOARD_SYSTEM76_GALP3_C
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_16384
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select DRIVERS_I2C_HID
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select EC_SYSTEM76_EC
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select EC_SYSTEM76_EC_BAT_THRESHOLDS
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select INTEL_GMA_HAVE_VBT
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_LPC_TPM
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select MAINBOARD_HAS_TPM2
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select NO_UART_ON_SUPERIO
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select PCIEXP_HOTPLUG
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select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G # Fix running out of MTRRs
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SOC_INTEL_WHISKEYLAKE
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select SPD_READ_BY_WORD
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select SYSTEM_TYPE_LAPTOP
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config MAINBOARD_DIR
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string
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default "system76/whl-u"
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config VARIANT_DIR
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string
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default "galp3-c" if BOARD_SYSTEM76_GALP3_C
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config OVERRIDE_DEVICETREE
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string
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default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
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config MAINBOARD_PART_NUMBER
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string
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default "galp3-c" if BOARD_SYSTEM76_GALP3_C
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config MAINBOARD_SMBIOS_PRODUCT_NAME
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string
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default "Galago Pro" if BOARD_SYSTEM76_GALP3_C
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config MAINBOARD_VERSION
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string
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default "galp3-c" if BOARD_SYSTEM76_GALP3_C
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config CBFS_SIZE
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hex
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default 0xA00000
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config CONSOLE_POST
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bool
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default y
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config ONBOARD_VGA_IS_PRIMARY
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bool
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default y
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config UART_FOR_CONSOLE
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int
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default 2
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config MAX_CPUS
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int
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default 8
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config DIMM_MAX
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int
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default 2
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config DIMM_SPD_SIZE
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int
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default 512
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config POST_DEVICE
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bool
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default n
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endif
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@ -0,0 +1,2 @@
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config BOARD_SYSTEM76_GALP3_C
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bool "galp3-c"
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@ -0,0 +1,8 @@
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
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bootblock-y += bootblock.c
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bootblock-y += gpio_early.c
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ramstage-y += ramstage.c
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ramstage-y += gpio.c
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ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
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@ -0,0 +1,11 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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// GPP_D9 SCI
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Method (_L29, 0, Serialized) {
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Debug = Concatenate("GPE _L29: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO))
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If (\_SB.PCI0.LPCB.EC0.ECOK) {
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If (\_SB.PCI0.LPCB.EC0.WFNO == 1) {
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Notify(\_SB.LID0, 0x80)
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}
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}
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}
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/* SPDX-License-Identifier: GPL-2.0-only */
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#define EC_GPE_SCI 0x50 /* GPP_E16 */
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#define EC_GPE_SWI 0x29 /* GPP_D9 */
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#include <ec/system76/ec/acpi/ec.asl>
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Scope (\_SB) {
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#include "sleep.asl"
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}
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Scope (\_GPE) {
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#include "gpe.asl"
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}
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#include "tbt.asl"
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Method called from _PTS prior to enter sleep state */
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Method (MPTS, 1) {
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\_SB.PCI0.LPCB.EC0.PTS (Arg0)
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}
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/* Method called from _WAK prior to wakeup */
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Method (MWAK, 1) {
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\_SB.PCI0.LPCB.EC0.WAK (Arg0)
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}
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/* SPDX-License-Identifier: GPL-2.0-only */
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// See https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-root-ports
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Scope(\_SB.PCI0.RP05) {
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Method(_DSD, 0, NotSerialized) {
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Return (Package(4) {
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// https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-root-ports#identifying-pcie-root-ports-supporting-hot-plug-in-d3
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ToUUID("6211e2c0-58a3-4af3-90e1-927a4e0c55a4"),
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Package(1) {
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Package(2) {
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"HotPlugSupportInD3",
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1
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}
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},
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// https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-root-ports#identifying-externally-exposed-pcie-root-ports
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ToUUID("efcc06cc-73ac-4bc3-bff0-76143807c389"),
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Package(2) {
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Package(2) {
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"ExternalFacingPort",
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1
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},
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Package(2) {
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"UID",
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0
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}
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}
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})
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}
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}
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@ -0,0 +1,8 @@
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Vendor name: System76
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Board name: whl-u
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Category: laptop
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Release year: 2019
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ROM package: SOIC-8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <gpio.h>
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#include <mainboard/gpio.h>
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void bootblock_mainboard_early_init(void)
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{
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mainboard_configure_early_gpios();
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}
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chip soc/intel/cannonlake
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# Lock Down
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 80,
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.fall_time_ns = 110,
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},
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}"
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# CPU (soc/intel/cannonlake/cpu.c)
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# Power limit
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register "power_limits_config" = "{
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.tdp_pl1_override = 20,
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.tdp_pl2_override = 30,
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}"
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# Enable Enhanced Intel SpeedStep
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register "eist_enable" = "1"
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# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
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register "SaGv" = "SaGv_Enabled"
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register "enable_c6dram" = "1"
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# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
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# Serial I/O
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register "SerialIoDevMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexUART2] = PchSerialIoPci,
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}"
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# Misc
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register "AcousticNoiseMitigation" = "1"
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# Power
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register "PchPmSlpS3MinAssert" = "3" # 50ms
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register "PchPmSlpS4MinAssert" = "1" # 1s
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register "PchPmSlpSusMinAssert" = "2" # 500ms
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register "PchPmSlpAMinAssert" = "4" # 2s
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# Thermal
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register "tcc_offset" = "12"
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# Serial IRQ Continuous
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register "serirq_mode" = "SERIRQ_CONTINUOUS"
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# PM Util (soc/intel/cannonlake/pmutil.c)
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "gpe0_dw0" = "PMC_GPP_C"
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register "gpe0_dw1" = "PMC_GPP_D"
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register "gpe0_dw2" = "PMC_GPP_E"
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# Actual device tree
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on # Integrated Graphics Device
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register "gfx" = "GMA_STATIC_DISPLAYS(0)"
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end
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device pci 04.0 on # SA Thermal device
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register "Device4Enable" = "1"
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end
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device pci 12.0 on end # Thermal Subsystem
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device pci 12.5 off end # UFS SCS
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device pci 12.6 off end # GSPI #2
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device pci 13.0 off end # Integrated Sensor Hub
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device pci 14.0 on # USB xHCI
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# USB2
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register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB-A
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register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # 3G / LTE
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register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C
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register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB-A
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register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
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# USB3
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-A
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G on galp3-c, NC on darp5
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-A
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register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Used by TBT
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register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Used by TBT
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end
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.3 on # CNVi wifi
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chip drivers/wifi/generic
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register "wake" = "PME_B0_EN_BIT"
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end
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end
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device pci 14.5 off end # SDCard
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device pci 15.0 on end # I2C #0
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device pci 15.1 off end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 16.0 off end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 16.5 off end # Management Engine Interface 4
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device pci 17.0 on # SATA
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register "SataPortsEnable[0]" = "1"
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register "SataPortsEnable[2]" = "1"
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end
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device pci 19.0 off end # I2C #4
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device pci 19.1 off end # I2C #5
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device pci 19.2 on end # UART #2
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device pci 1a.0 off end # eMMC
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device pci 1c.0 on end # PCI Express Port 1
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device pci 1c.1 off end # PCI Express Port 2
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device pci 1c.2 off end # PCI Express Port 3
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device pci 1c.3 off end # PCI Express Port 4
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device pci 1c.4 on # PCI Express Port 5
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# PCI Express Root port #5 x4, Clock 4 (TBT)
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register "PcieRpEnable[4]" = "1"
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register "PcieRpLtrEnable[4]" = "1"
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register "PcieRpHotPlug[4]" = "1"
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register "PcieClkSrcUsage[4]" = "4"
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register "PcieClkSrcClkReq[4]" = "4"
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end
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device pci 1c.5 off end # PCI Express Port 6
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device pci 1c.6 off end # PCI Express Port 7
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device pci 1c.7 off end # PCI Express Port 8
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device pci 1d.0 on # PCI Express Port 9
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# PCI Express Root port #9 x1, Clock 3 (LAN)
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register "PcieRpEnable[8]" = "1"
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register "PcieRpLtrEnable[8]" = "1"
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register "PcieClkSrcUsage[3]" = "8"
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register "PcieClkSrcClkReq[3]" = "3"
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end
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device pci 1d.1 on # PCI Express Port 10
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# PCI Express Root port #10 x1, Clock 2 (WLAN)
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register "PcieRpEnable[9]" = "1"
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register "PcieRpLtrEnable[9]" = "0"
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register "PcieClkSrcUsage[2]" = "9"
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register "PcieClkSrcClkReq[2]" = "2"
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end
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device pci 1d.2 off end # PCI Express Port 11
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device pci 1d.3 off end # PCI Express Port 12
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device pci 1d.4 on # PCI Express Port 13
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# PCI Express Root port #13 x4, Clock 5 (NVMe)
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register "PcieRpEnable[12]" = "1"
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register "PcieRpLtrEnable[12]" = "1"
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register "PcieClkSrcUsage[5]" = "12"
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register "PcieClkSrcClkReq[5]" = "5"
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end
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device pci 1d.5 off end # PCI Express Port 14
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device pci 1d.6 off end # PCI Express Port 15
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device pci 1d.7 off end # PCI Express Port 16
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device pci 1e.0 off end # UART #0
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device pci 1e.1 off end # UART #1
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device pci 1e.2 off end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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device pci 1f.0 on # LPC Interface
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register "gen1_dec" = "0x000c0081"
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register "gen2_dec" = "0x00040069"
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register "gen3_dec" = "0x00fc0e01"
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register "gen4_dec" = "0x00fc0f01"
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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end
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device pci 1f.1 off end # P2SB
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device pci 1f.2 off end # Power Management Controller
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device pci 1f.3 on # Intel HDA
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register "PchHdaAudioLinkHda" = "1"
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register "PchHdaAudioLinkDmic0" = "1"
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register "PchHdaAudioLinkDmic1" = "1"
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end
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # PCH SPI
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device pci 1f.6 off end # GbE
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end
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end
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725 /* OEM revision */
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)
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{
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#include <acpi/dsdt_top.asl>
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#include <soc/intel/common/block/acpi/acpi/platform.asl>
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#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
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#include <cpu/intel/common/acpi/cpu.asl>
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Device (\_SB.PCI0)
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{
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#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
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#include <soc/intel/cannonlake/acpi/southbridge.asl>
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#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
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}
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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Scope (\_SB.PCI0.LPCB)
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{
|
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#include <drivers/pc80/pc/ps2_controller.asl>
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}
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#include "acpi/mainboard.asl"
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}
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|
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@ -0,0 +1,218 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
|
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|
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#include <mainboard/gpio.h>
|
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#include <soc/gpe.h>
|
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#include <soc/gpio.h>
|
||||
|
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static const struct pad_config gpio_table[] = {
|
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/* ------- GPIO Group GPD ------- */
|
||||
PAD_CFG_GPI(GPD0, NONE, DEEP), // PM_BATLOW#
|
||||
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
|
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PAD_NC(GPD2, NONE),
|
||||
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
|
||||
PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
|
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PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
|
||||
PAD_NC(GPD6, NONE),
|
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PAD_NC(GPD7, NONE), // 100k pull up
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK
|
||||
PAD_CFG_GPO(GPD9, 0, DEEP), // GPD9_RTD3 on galp3-c, NC on darp5
|
||||
PAD_NC(GPD10, NONE),
|
||||
PAD_NC(GPD11, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_A ------- */
|
||||
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST#
|
||||
PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // LPC_AD0
|
||||
PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // LPC_AD1
|
||||
PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // LPC_AD2
|
||||
PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // LPC_AD3
|
||||
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ with 10k pull up
|
||||
PAD_CFG_GPI(GPP_A7, NONE, DEEP), // TPM_PIRQ#
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN# with 8.2k pull-up
|
||||
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // PCLK_KBC
|
||||
PAD_NC(GPP_A10, NONE),
|
||||
PAD_NC(GPP_A11, NONE),
|
||||
PAD_NC(GPP_A12, NONE), // 10k pull up
|
||||
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN#
|
||||
PAD_NC(GPP_A14, NONE),
|
||||
PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), // SUS_PWR_ACK
|
||||
PAD_NC(GPP_A16, NONE),
|
||||
PAD_CFG_GPI(GPP_A17, NONE, DEEP), // LIGHT_KB_DET#
|
||||
PAD_NC(GPP_A18, NONE),
|
||||
PAD_CFG_GPO(GPP_A19, 1, DEEP), // SATA_PWR_EN
|
||||
PAD_NC(GPP_A20, NONE),
|
||||
PAD_NC(GPP_A21, NONE),
|
||||
PAD_CFG_GPO(GPP_A22, 0, DEEP), // PS8338B_SW
|
||||
PAD_CFG_GPO(GPP_A23, 0, DEEP), // PS8338B_PCH
|
||||
|
||||
/* ------- GPIO Group GPP_B ------- */
|
||||
PAD_NC(GPP_B0, NONE), // CORE_VID0
|
||||
PAD_NC(GPP_B1, NONE), // CORE_VID1
|
||||
PAD_CFG_GPI(GPP_B2, NONE, DEEP), // CNVI_WAKE#
|
||||
PAD_NC(GPP_B3, NONE),
|
||||
PAD_NC(GPP_B4, NONE),
|
||||
PAD_NC(GPP_B5, NONE),
|
||||
PAD_NC(GPP_B6, NONE),
|
||||
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // WLAN_CLKREQ#
|
||||
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), // LAN_CLKREQ#
|
||||
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), // TBT_CLKREQ#
|
||||
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // SSD_CLKREQ#
|
||||
PAD_NC(GPP_B11, NONE),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
|
||||
PAD_NC(GPP_B15, NONE),
|
||||
PAD_NC(GPP_B16, NONE),
|
||||
PAD_NC(GPP_B17, NONE),
|
||||
PAD_CFG_GPI(GPP_B18, NONE, DEEP), // T16 on galp3-c, NO REBOOT STRAP on darp5
|
||||
PAD_NC(GPP_B19, NONE),
|
||||
PAD_NC(GPP_B20, NONE),
|
||||
PAD_NC(GPP_B21, NONE),
|
||||
PAD_NC(GPP_B22, NONE), // 20k pull down on galp3-c, T14 on darp5
|
||||
PAD_NC(GPP_B23, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_C ------- */
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK_DDR
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DAT_DDR
|
||||
PAD_NC(GPP_C2, NONE), // 4.7k pull-up
|
||||
PAD_NC(GPP_C3, NONE),
|
||||
PAD_NC(GPP_C4, NONE),
|
||||
PAD_CFG_GPI(GPP_C5, NONE, DEEP), // 4.7k pull down on galp3-c, WLAN_WAKEUP# on darp5
|
||||
PAD_CFG_GPI(GPP_C6, NONE, DEEP), // LAN_WAKEUP# on galp3-c, NC on darp5
|
||||
PAD_NC(GPP_C7, NONE),
|
||||
PAD_NC(GPP_C8, NONE),
|
||||
PAD_CFG_GPI_SCI_LOW(GPP_C9, UP_20K, PLTRST, EDGE_SINGLE), // TBCIO_PLUG_EVENT
|
||||
PAD_CFG_GPO(GPP_C10, 1, PLTRST), // TBT_FRC_PWR
|
||||
PAD_NC(GPP_C11, NONE),
|
||||
PAD_CFG_GPO(GPP_C12, 1, PLTRST), // GPP_C12_RTD3
|
||||
PAD_CFG_GPO(GPP_C13, 1, PLTRST), // SSD_PWR_DN#
|
||||
PAD_CFG_GPO(GPP_C14, 0, PLTRST), // TBTA_HRESET
|
||||
PAD_CFG_TERM_GPO(GPP_C15, 1, UP_20K, PLTRST), // TBT_PERST_N
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // T_SDA
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // T_SCL
|
||||
PAD_NC(GPP_C18, NONE),
|
||||
PAD_CFG_GPI(GPP_C19, NONE, DEEP), // SWI# on galp3-c, NC on darp5
|
||||
//PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
|
||||
//PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
|
||||
PAD_NC(GPP_C22, NONE),
|
||||
PAD_CFG_GPI_APIC_EDGE_LOW(GPP_C23, NONE, PLTRST), // NC on galp3-c, TP_ATTN# on darp5
|
||||
|
||||
/* ------- GPIO Group GPP_D ------- */
|
||||
PAD_NC(GPP_D0, NONE),
|
||||
PAD_NC(GPP_D1, NONE),
|
||||
PAD_NC(GPP_D2, NONE),
|
||||
PAD_NC(GPP_D3, NONE),
|
||||
PAD_NC(GPP_D4, NONE),
|
||||
PAD_NC(GPP_D5, NONE),
|
||||
PAD_NC(GPP_D6, NONE),
|
||||
PAD_NC(GPP_D7, NONE),
|
||||
PAD_CFG_GPO(GPP_D8, 1, DEEP), // SB_BLON
|
||||
PAD_CFG_GPI_SCI_LOW(GPP_D9, NONE, DEEP, LEVEL), // SWI#
|
||||
PAD_NC(GPP_D10, NONE),
|
||||
PAD_CFG_GPI_SCI_LOW(GPP_D11, UP_20K, DEEP, LEVEL), // RTD3_PCIE_WAKE#
|
||||
PAD_NC(GPP_D12, NONE), // 100k pull up on galp3-c, NC on darp5
|
||||
PAD_NC(GPP_D13, NONE),
|
||||
PAD_NC(GPP_D14, NONE),
|
||||
PAD_NC(GPP_D15, NONE),
|
||||
PAD_CFG_GPO(GPP_D16, 1, PWROK), // RTD3_3G_PW R_EN
|
||||
PAD_NC(GPP_D17, NONE),
|
||||
PAD_NC(GPP_D18, NONE),
|
||||
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // GPPC_DMIC_CLK
|
||||
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // GPPC_DMIC_DATA
|
||||
PAD_CFG_GPI(GPP_D21, NONE, DEEP), // TPM_DET#
|
||||
PAD_CFG_GPI(GPP_D22, NONE, DEEP), // TPM_TCM_Detect
|
||||
PAD_NC(GPP_D23, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_E ------- */
|
||||
PAD_NC(GPP_E0, NONE), // PCH_GPP_E0 10k pull up
|
||||
PAD_NC(GPP_E1, NONE), // SATA_ODD_PRSNT#
|
||||
PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1), // SATAGP2
|
||||
PAD_NC(GPP_E3, NONE),
|
||||
PAD_NC(GPP_E4, NONE),
|
||||
PAD_NC(GPP_E5, NONE),
|
||||
PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), // DEVSLP2
|
||||
PAD_NC(GPP_E7, NONE),
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATAHDD_LED#
|
||||
PAD_NC(GPP_E9, NONE), // GP_BSSB_CLK
|
||||
PAD_NC(GPP_E10, NONE),
|
||||
PAD_NC(GPP_E11, NONE),
|
||||
PAD_NC(GPP_E12, NONE), // USB_OC#78
|
||||
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), // MUX_HPD
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // HDMI_HPD
|
||||
PAD_CFG_GPI_SMI_LOW(GPP_E15, NONE, DEEP, EDGE_SINGLE), // SMI#
|
||||
PAD_CFG_GPI_SCI_LOW(GPP_E16, NONE, DEEP, LEVEL), // SCI#
|
||||
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), // EDP_HPD
|
||||
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), // MDP_CTRLCLK
|
||||
PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), // MDP_CTRLDATA
|
||||
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), // HDMI_CTRLCLK
|
||||
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), // HDMI_CTRLDATA
|
||||
PAD_NC(GPP_E22, NONE),
|
||||
PAD_NC(GPP_E23, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_F ------- */
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
|
||||
PAD_NC(GPP_F1, NONE),
|
||||
PAD_NC(GPP_F2, NONE),
|
||||
PAD_NC(GPP_F3, NONE),
|
||||
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_BRI_DT
|
||||
PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_RGI_DT
|
||||
PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
|
||||
PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
|
||||
PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
|
||||
PAD_NC(GPP_F10, NONE),
|
||||
PAD_NC(GPP_F11, NONE),
|
||||
PAD_NC(GPP_F12, NONE),
|
||||
PAD_NC(GPP_F13, NONE),
|
||||
PAD_NC(GPP_F14, NONE),
|
||||
PAD_NC(GPP_F15, NONE),
|
||||
PAD_NC(GPP_F16, NONE),
|
||||
PAD_NC(GPP_F17, NONE),
|
||||
PAD_NC(GPP_F18, NONE),
|
||||
PAD_NC(GPP_F19, NONE),
|
||||
PAD_NC(GPP_F20, NONE),
|
||||
PAD_NC(GPP_F21, NONE),
|
||||
PAD_NC(GPP_F22, NONE),
|
||||
PAD_CFG_GPI(GPP_F23, NONE, DEEP), // A4WP_PRESENT
|
||||
|
||||
/* ------- GPIO Group GPP_G ------- */
|
||||
PAD_CFG_GPI(GPP_G0, NONE, DEEP), // EDP_DET on galp3-c, NC on darp5
|
||||
PAD_NC(GPP_G1, NONE),
|
||||
PAD_NC(GPP_G2, NONE),
|
||||
PAD_CFG_GPO(GPP_G3, 0, DEEP), // ASM1543_I_SEL0 on galp3-c, NC on darp5
|
||||
PAD_CFG_GPO(GPP_G4, 0, DEEP), // ASM1543_I_SEL1 on galp3-c, NC on darp5
|
||||
PAD_CFG_GPI(GPP_G5, NONE, DEEP), // BOARD_ID
|
||||
PAD_NC(GPP_G6, NONE),
|
||||
PAD_CFG_GPI(GPP_G7, NONE, DEEP), // TBT_Detect
|
||||
|
||||
/* ------- GPIO Group GPP_H ------- */
|
||||
PAD_NC(GPP_H0, NONE),
|
||||
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), // CNVI_RST#
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), // CNVI_CLKREQ
|
||||
PAD_NC(GPP_H3, NONE),
|
||||
PAD_NC(GPP_H4, NONE),
|
||||
PAD_NC(GPP_H5, NONE),
|
||||
PAD_NC(GPP_H6, NONE),
|
||||
PAD_NC(GPP_H7, NONE),
|
||||
PAD_NC(GPP_H8, NONE),
|
||||
PAD_NC(GPP_H9, NONE),
|
||||
PAD_NC(GPP_H10, NONE),
|
||||
PAD_NC(GPP_H11, NONE),
|
||||
PAD_NC(GPP_H12, NONE),
|
||||
PAD_NC(GPP_H13, NONE),
|
||||
PAD_NC(GPP_H14, NONE), // G_INT1 10k pull up
|
||||
PAD_NC(GPP_H15, NONE),
|
||||
PAD_NC(GPP_H16, NONE),
|
||||
PAD_NC(GPP_H17, NONE),
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
|
||||
PAD_NC(GPP_H19, NONE),
|
||||
PAD_NC(GPP_H20, NONE),
|
||||
PAD_CFG_GPI(GPP_H21, NONE, DEEP), // GPPC_H21; LOW: 38.4/19.2M, HI: 24M
|
||||
PAD_CFG_GPO(GPP_H22, 1, PLTRST), // TBT_RTD3_PWR_EN_R
|
||||
PAD_CFG_GPI(GPP_H23, NONE, DEEP), // WIGIG_PEWAKE on galp3-c, NC on darp5
|
||||
};
|
||||
|
||||
void mainboard_configure_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <mainboard/gpio.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
|
||||
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
|
||||
};
|
||||
|
||||
void mainboard_configure_early_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
|
||||
}
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
void mainboard_configure_early_gpios(void);
|
||||
void mainboard_configure_gpios(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/device.h>
|
||||
#include <mainboard/gpio.h>
|
||||
|
||||
static void mainboard_init(void *chip_info)
|
||||
{
|
||||
mainboard_configure_gpios();
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.init = mainboard_init,
|
||||
};
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/cnl_memcfg_init.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
static const struct cnl_mb_cfg memcfg = {
|
||||
.spd[0] = {
|
||||
.read_type = READ_SMBUS,
|
||||
.spd_spec = {.spd_smbus_address = 0xa0},
|
||||
},
|
||||
.spd[2] = {
|
||||
.read_type = READ_SMBUS,
|
||||
.spd_spec = {.spd_smbus_address = 0xa4},
|
||||
},
|
||||
.rcomp_resistor = { 121, 81, 100 },
|
||||
.rcomp_targets = { 100, 40, 20, 20, 26 },
|
||||
.dq_pins_interleaved = 1,
|
||||
.vref_ca_config = 2,
|
||||
};
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *memupd)
|
||||
{
|
||||
cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
|
||||
}
|
||||
|
|
@ -0,0 +1 @@
|
|||
Board name: galp3-c
|
||||
Binary file not shown.
|
|
@ -0,0 +1,35 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek ALC293 */
|
||||
0x10ec0293, /* Vendor ID */
|
||||
0x15581323, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x15581323),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x02211020),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x02a11040),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40738205),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
|
||||
/* Intel GPU HDMI */
|
||||
0x8086280b, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
4, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x05, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x07, 0x18560010),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
chip soc/intel/cannonlake
|
||||
device domain 0 on
|
||||
subsystemid 0x1558 0x1323 inherit
|
||||
device pci 15.0 on
|
||||
# I2C HID not supported on galp3-c
|
||||
end # I2C #0
|
||||
end
|
||||
end
|
||||
Loading…
Reference in New Issue