GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/cannonlake: Add configs for USB 3.1 Gen2 EV settings 

Add configs for USB 3.1 Gen2 EV settings so that people can set the
EV settings per board in device tree.

BUG=b:150515720
BRANCH=none
TEST=build coreboot and fsp with enabled fw_debug.
     Flashed to puff and checked the log.
     All usb configs were set correctly.

Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Change-Id: Id4860665619095139c329565d433d9eb495cac02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39448
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jamie Chen 2020-03-10 16:50:53 +08:00 committed by Edward O'Callaghan
parent 73e35f6af9
commit 3658c62908
2 changed files with 81 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
src/soc/intel/cannonlake/fsp_params.c
View File

@ -404,6 +404,36 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->Usb3HsioTxDownscaleAmp[i] = params->Usb3HsioTxDownscaleAmp[i] =
config->usb3_ports[i].tx_downscale_amp; config->usb3_ports[i].tx_downscale_amp;
} }
#if CONFIG(SOC_INTEL_COMETLAKE)
if (config->usb3_ports[i].gen2_tx_rate0_uniq_tran_enable) {
params->Usb3HsioTxRate0UniqTranEnable[i] = 1;
params->Usb3HsioTxRate0UniqTran[i] =
config->usb3_ports[i].gen2_tx_rate0_uniq_tran;
}
if (config->usb3_ports[i].gen2_tx_rate1_uniq_tran_enable) {
params->Usb3HsioTxRate1UniqTranEnable[i] = 1;
params->Usb3HsioTxRate1UniqTran[i] =
config->usb3_ports[i].gen2_tx_rate1_uniq_tran;
}
if (config->usb3_ports[i].gen2_tx_rate2_uniq_tran_enable) {
params->Usb3HsioTxRate2UniqTranEnable[i] = 1;
params->Usb3HsioTxRate2UniqTran[i] =
config->usb3_ports[i].gen2_tx_rate2_uniq_tran;
}
if (config->usb3_ports[i].gen2_tx_rate3_uniq_tran_enable) {
params->Usb3HsioTxRate3UniqTranEnable[i] = 1;
params->Usb3HsioTxRate3UniqTran[i] =
config->usb3_ports[i].gen2_tx_rate3_uniq_tran;
}
#endif
if (config->usb3_ports[i].gen2_rx_tuning_enable) {
params->PchUsbHsioRxTuningEnable[i] =
config->usb3_ports[i].gen2_rx_tuning_enable;
params->PchUsbHsioRxTuningParameters[i] =
config->usb3_ports[i].gen2_rx_tuning_params;
params->PchUsbHsioFilterSel[i] =
config->usb3_ports[i].gen2_rx_filter_sel;
}
} }
/* Enable xDCI controller if enabled in devicetree and allowed */ /* Enable xDCI controller if enabled in devicetree and allowed */

51
src/soc/intel/cannonlake/include/soc/usb.h
View File

@ -120,6 +120,17 @@ struct usb3_port_config {
uint8_t ocpin; uint8_t ocpin;
uint8_t tx_de_emp; uint8_t tx_de_emp;
uint8_t tx_downscale_amp; uint8_t tx_downscale_amp;
uint8_t gen2_tx_rate0_uniq_tran_enable;
uint8_t gen2_tx_rate0_uniq_tran;
uint8_t gen2_tx_rate1_uniq_tran_enable;
uint8_t gen2_tx_rate1_uniq_tran;
uint8_t gen2_tx_rate2_uniq_tran_enable;
uint8_t gen2_tx_rate2_uniq_tran;
uint8_t gen2_tx_rate3_uniq_tran_enable;
uint8_t gen2_tx_rate3_uniq_tran;
uint8_t gen2_rx_tuning_enable;
uint8_t gen2_rx_tuning_params;
uint8_t gen2_rx_filter_sel;
}; };
#define USB3_PORT_EMPTY { \ #define USB3_PORT_EMPTY { \
@ -127,6 +138,17 @@ struct usb3_port_config {
.ocpin = OC_SKIP, \ .ocpin = OC_SKIP, \
.tx_de_emp = 0x00, \ .tx_de_emp = 0x00, \
.tx_downscale_amp = 0x00, \ .tx_downscale_amp = 0x00, \
.gen2_tx_rate0_uniq_tran_enable = 0, \
.gen2_tx_rate0_uniq_tran = 0x00, \
.gen2_tx_rate1_uniq_tran_enable = 0, \
.gen2_tx_rate1_uniq_tran = 0x00, \
.gen2_tx_rate2_uniq_tran_enable = 0, \
.gen2_tx_rate2_uniq_tran = 0x00, \
.gen2_tx_rate3_uniq_tran_enable = 0, \
.gen2_tx_rate3_uniq_tran = 0x00, \
.gen2_rx_tuning_enable = 0, \
.gen2_rx_tuning_params = 0x00, \
.gen2_rx_filter_sel = 0x00, \
} }
#define USB3_PORT_DEFAULT(pin) { \ #define USB3_PORT_DEFAULT(pin) { \
@ -134,6 +156,35 @@ struct usb3_port_config {
.ocpin = (pin), \ .ocpin = (pin), \
.tx_de_emp = 0x0, \ .tx_de_emp = 0x0, \
.tx_downscale_amp = 0x00, \ .tx_downscale_amp = 0x00, \
.gen2_tx_rate0_uniq_tran_enable = 0, \
.gen2_tx_rate0_uniq_tran = 0x00, \
.gen2_tx_rate1_uniq_tran_enable = 0, \
.gen2_tx_rate1_uniq_tran = 0x00, \
.gen2_tx_rate2_uniq_tran_enable = 0, \
.gen2_tx_rate2_uniq_tran = 0x00, \
.gen2_tx_rate3_uniq_tran_enable = 0, \
.gen2_tx_rate3_uniq_tran = 0x00, \
.gen2_rx_tuning_enable = 0, \
.gen2_rx_tuning_params = 0x00, \
.gen2_rx_filter_sel = 0x00, \
}
#define USB3_PORT_GEN2_DEFAULT(pin) { \
.enable = 1, \
.ocpin = (pin), \
.tx_de_emp = 0x0, \
.tx_downscale_amp = 0x00, \
.gen2_tx_rate0_uniq_tran_enable = 0, \
.gen2_tx_rate0_uniq_tran = 0x00, \
.gen2_tx_rate1_uniq_tran_enable = 0, \
.gen2_tx_rate1_uniq_tran = 0x00, \
.gen2_tx_rate2_uniq_tran_enable = 1, \
.gen2_tx_rate2_uniq_tran = 0x4C, \
.gen2_tx_rate3_uniq_tran_enable = 0, \
.gen2_tx_rate3_uniq_tran = 0x00, \
.gen2_rx_tuning_enable = 0x0F, \
.gen2_rx_tuning_params = 0x15, \
.gen2_rx_filter_sel = 0x44, \
} }
/* /*