soc/intel/apollolake: Add support for GSPI
BUG=b:73133848 BRANCH=None TEST=Build coreboot for Octopus board. Tested the GSPI interface with a SPI EEPROM and got correct response to a RDID command Change-Id: Iec96f926ba7162074090617b7cf1c84e36b0fb37 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/24906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -9,6 +9,7 @@ config SOC_INTEL_GLK
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select SOC_INTEL_APOLLOLAKE
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select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
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select SOC_INTEL_COMMON_BLOCK_SGX
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select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
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help
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Intel GLK support
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@ -374,4 +375,8 @@ config SOC_ESPI
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help
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Use eSPI bus instead of LPC
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config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
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int
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default 3
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endif
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@ -11,6 +11,7 @@ subdirs-y += ../../../cpu/x86/cache
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bootblock-y += bootblock/bootblock.c
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bootblock-y += car.c
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bootblock-y += heci.c
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bootblock-y += gspi.c
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bootblock-y += i2c.c
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bootblock-y += lpc.c
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bootblock-y += mmap_boot.c
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@ -21,6 +22,7 @@ bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S
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romstage-y += car.c
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romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
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romstage-y += gspi.c
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romstage-y += heci.c
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romstage-y += i2c.c
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romstage-$(CONFIG_SOC_UART_DEBUG) += uart.c
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@ -48,6 +50,7 @@ ramstage-y += chip.c
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ramstage-y += cse.c
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ramstage-y += elog.c
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ramstage-y += graphics.c
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ramstage-y += gspi.c
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ramstage-y += heci.c
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ramstage-y += i2c.c
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ramstage-y += lpc.c
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@ -73,6 +76,7 @@ postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S
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verstage-y += car.c
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verstage-y += i2c.c
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verstage-y += gspi.c
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verstage-y += heci.c
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verstage-y += memmap.c
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verstage-y += mmap_boot.c
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@ -20,6 +20,7 @@
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#define _SOC_APOLLOLAKE_CHIP_H_
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#include <commonlib/helpers.h>
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#include <intelblocks/gspi.h>
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#include <soc/gpe.h>
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#include <soc/gpio.h>
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#include <intelblocks/lpc_lib.h>
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@ -39,6 +40,9 @@ enum pnp_settings {
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};
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struct soc_intel_apollolake_config {
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/* GSPI */
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struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
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/*
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* Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has
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* four CLKREQ inputs, but six root ports. Root ports without an
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@ -0,0 +1,73 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <intelblocks/gspi.h>
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#include <intelblocks/spi.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include "chip.h"
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const struct gspi_cfg *gspi_get_soc_cfg(void)
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{
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DEVTREE_CONST struct soc_intel_apollolake_config *config;
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int devfn = SA_DEVFN_ROOT;
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DEVTREE_CONST struct device *dev = dev_find_slot(0, devfn);
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if (!dev || !dev->chip_info) {
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printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
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__func__);
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return NULL;
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}
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config = dev->chip_info;
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return &config->gspi[0];
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}
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uintptr_t gspi_get_soc_early_base(void)
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{
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return EARLY_GSPI_BASE_ADDRESS;
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}
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/*
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* SPI Bus 0 is Fast SPI and GSPI starts from SPI bus # 1 onwards. Thus, adjust
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* the bus # accordingly when referring to SPI / GSPI bus numbers.
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*/
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#define GSPI_TO_SPI_BUS(x) (x)
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#define SPI_TO_GSPI_BUS(x) ((x) - 1)
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int gspi_soc_spi_to_gspi_bus(unsigned int spi_bus, unsigned int *gspi_bus)
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{
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if (spi_bus == 0)
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return -1;
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if (SPI_TO_GSPI_BUS(spi_bus) >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)
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return -1;
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*gspi_bus = SPI_TO_GSPI_BUS(spi_bus);
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return 0;
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}
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int gspi_soc_bus_to_devfn(unsigned int gspi_bus)
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{
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if (gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)
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return -1;
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return spi_soc_bus_to_devfn(GSPI_TO_SPI_BUS(gspi_bus));
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}
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@ -48,6 +48,7 @@
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/* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */
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#define PRERAM_SPI_BASE_ADDRESS 0xfe010000
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#define EARLY_GSPI_BASE_ADDRESS 0xfe011000
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/* Temporary BAR for early I2C bus access */
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#define PRERAM_I2C_BASE_ADDRESS(x) (0xfe020000 + (0x1000 * (x)))
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