ec/google/chromec: Add DPTC support for host event 1/2/9
DTTS is Dynamic Thermal Table Switching Proposal. Add DPTC support for host event lid-open/lid-close/Thermal Threshold. BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I156a9d138ccac7f75cc0dd0d827f7a721fcbc782 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67793 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
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@ -229,6 +229,11 @@ Device (EC0)
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Method (_Q01, 0, NotSerialized)
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{
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Printf ("EC: LID CLOSE")
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#if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)
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If (CondRefOf (\_SB.DPTC)) {
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\_SB.DPTC()
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}
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#endif
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Store (LIDS, \LIDS)
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#ifdef EC_ENABLE_LID_SWITCH
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Notify (LID0, 0x80)
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@ -239,6 +244,11 @@ Device (EC0)
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Method (_Q02, 0, NotSerialized)
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{
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Printf ("EC: LID OPEN")
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#if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)
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If (CondRefOf (\_SB.DPTC)) {
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\_SB.DPTC()
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}
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#endif
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Store (LIDS, \LIDS)
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Notify (CREC, 0x2)
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#ifdef EC_ENABLE_LID_SWITCH
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@ -540,6 +550,12 @@ Device (EC0)
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*/
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Method (_Q09, 0, NotSerialized)
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{
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#if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)
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If (CondRefOf (\_SB.DPTC)) {
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\_SB.DPTC()
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}
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#endif
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If (!Acquire (^PATM, 1000)) {
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/* Read sensor ID for event */
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Store (^PATI, Local0)
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