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mb/google/brya: Add GPIO_IN_RW to all variants' early GPIO tables 

Before attempting another commit 6260bf71 ("vboot_logic: Set
VB2_CONTEXT_EC_TRUSTED in verstage_main"), ensure that brya's variants
all program EC_IN_RW as an input GPIO in bootblock so that it can be read
from in verstage.

Change-Id: I6b1af50f257dc7b627c4c00d7480ba7732c3d1a0
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
This commit is contained in:
Tim Wawrzynczak 2021-10-07 16:02:11 -06:00
parent 3394f4a8f6
commit 36721a483b
9 changed files with 20 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/brya/variants/anahera/gpio.c
View File

@ -118,6 +118,8 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
/* E16 : RSVD_TP ==> WWAN_RST_L */
PAD_CFG_GPO(GPP_E16, 0, DEEP),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */

2
src/mainboard/google/brya/variants/brask/gpio.c
View File

@ -27,6 +27,8 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPO(GPP_D2, 1, DEEP),
/* E15 : RSVD_TP ==> PCH_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */

4
src/mainboard/google/brya/variants/brya0/gpio.c
View File

@ -58,6 +58,8 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPO(GPP_E16, 0, DEEP),
/* E15 : RSVD_TP ==> PCH_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
/* F21 : EXT_PWR_GATE2# ==> NC */
PAD_NC(GPP_F21, NONE),
/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
@ -101,6 +103,8 @@ static const struct pad_config early_gpio_table_id2[] = {
PAD_CFG_GPO(GPP_E16, 0, DEEP),
/* E15 : RSVD_TP ==> PCH_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */
PAD_CFG_GPO(GPP_F21, 0, DEEP),
/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */

2
src/mainboard/google/brya/variants/felwinter/gpio.c
View File

@ -127,6 +127,8 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPI(GPP_E13, NONE, DEEP),
/* E15 : RSVD_TP ==> PCH_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */

2
src/mainboard/google/brya/variants/gimble/gpio.c
View File

@ -143,6 +143,8 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
/* E16 : RSVD_TP ==> NC */
PAD_NC(GPP_E16, NONE),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */

2
src/mainboard/google/brya/variants/kano/gpio.c
View File

@ -124,6 +124,8 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPI(GPP_E13, NONE, DEEP),
/* E15 : RSVD_TP ==> PCH_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */

2
src/mainboard/google/brya/variants/primus/gpio.c
View File

@ -106,6 +106,8 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPO(GPP_E16, 0, DEEP),
/* E15 : RSVD_TP ==> PCH_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */

2
src/mainboard/google/brya/variants/redrix/gpio.c
View File

@ -100,6 +100,8 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
/* E16 : RSVD_TP ==> WWAN_RST_L */
PAD_CFG_GPO(GPP_E16, 0, DEEP),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */

2
src/mainboard/google/brya/variants/taeko/gpio.c
View File

@ -162,6 +162,8 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPI(GPP_E13, NONE, DEEP),
/* E15 : RSVD_TP ==> PCH_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */