libpayload: mips: add SOC CPU frequency
Add CPU frequency corresponding to SOC. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; behaves as expected. BRANCH=none Change-Id: I05458070a15c6cf1ef0fc2104715a63902a38887 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4afe332bcc41afeb7e31e918e345c3336f7dc604 Original-Change-Id: I55b788faf7984bafc2509cac69867a772c7cb863 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241427 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8853 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -19,6 +19,10 @@
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#include <libpayload.h>
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#include <libpayload.h>
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#include <arch/cpu.h>
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#include <arch/cpu.h>
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#include <arch/io.h>
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#define PISTACHIO_CLOCK_SWITCH 0xB8144200
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#define MIPS_EXTERN_PLL_BYPASS_MASK 0x00000002
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/**
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/**
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* @ingroup arch
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* @ingroup arch
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@ -34,10 +38,19 @@ u32 cpu_khz;
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unsigned int get_cpu_speed(void)
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unsigned int get_cpu_speed(void)
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{
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{
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if (IMG_PLATFORM_ID() != IMG_PLATFORM_ID_SILICON)
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if (IMG_PLATFORM_ID() != IMG_PLATFORM_ID_SILICON)
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cpu_khz = 50000U; /* FPGA board */
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cpu_khz = 50000; /* FPGA board */
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/* else {
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else {
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* TODO find CPU frequency on the real SOC
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/* If MIPS PLL external bypass bit is set, it means
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} */
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* that the MIPS PLL is already set up to work at a
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* frequency of 550 MHz; otherwise, the crystal is
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* used with a frequency of 52 MHz
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*/
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if (read32(PISTACHIO_CLOCK_SWITCH) &
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MIPS_EXTERN_PLL_BYPASS_MASK)
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cpu_khz = 550000;
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else
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cpu_khz = 52000;
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}
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return cpu_khz;
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return cpu_khz;
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}
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}
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