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libpayload: mips: add SOC CPU frequency 

Add CPU frequency corresponding to SOC.

BUG=chrome-os-partner:31438
TEST=tested on Pistachio bring up board; behaves as expected.
BRANCH=none

Change-Id: I05458070a15c6cf1ef0fc2104715a63902a38887
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4afe332bcc41afeb7e31e918e345c3336f7dc604
Original-Change-Id: I55b788faf7984bafc2509cac69867a772c7cb863
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/241427
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8853
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Ionela Voinescu 2015-01-19 02:41:49 +00:00 committed by Patrick Georgi
parent bde2081e75
commit 3673311619
1 changed files with 17 additions and 4 deletions
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21
payloads/libpayload/arch/mips/timer.c
View File

@ -19,6 +19,10 @@
#include <libpayload.h>
#include <arch/cpu.h>
#include <arch/io.h>
#define PISTACHIO_CLOCK_SWITCH 0xB8144200
#define MIPS_EXTERN_PLL_BYPASS_MASK 0x00000002
/**
* @ingroup arch
@ -34,10 +38,19 @@ u32 cpu_khz;
unsigned int get_cpu_speed(void)
{
if (IMG_PLATFORM_ID() != IMG_PLATFORM_ID_SILICON)
cpu_khz = 50000U; /* FPGA board */
/* else {
* TODO find CPU frequency on the real SOC
} */
cpu_khz = 50000; /* FPGA board */
else {
/* If MIPS PLL external bypass bit is set, it means
* that the MIPS PLL is already set up to work at a
* frequency of 550 MHz; otherwise, the crystal is
* used with a frequency of 52 MHz
*/
if (read32(PISTACHIO_CLOCK_SWITCH) &
MIPS_EXTERN_PLL_BYPASS_MASK)
cpu_khz = 550000;
else
cpu_khz = 52000;
}
return cpu_khz;
}