mb/google/brya/variants/gimble: Update audio setting
Add vmon-slot-no,imon-slot-no and dsm_param_file_name in overridetree.cb BUG=b:197701952 TEST=build and check SSDT Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ie646360c4ebbf25762b374c5bc3ef2017989fb2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57832 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -124,6 +124,9 @@ chip soc/intel/alderlake
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register "name" = ""MXW0""
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register "name" = ""MXW0""
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register "r0_calib_key" = ""dsm_calib_r0_0""
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register "r0_calib_key" = ""dsm_calib_r0_0""
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register "temperature_calib_key" = ""dsm_calib_temp_0""
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register "temperature_calib_key" = ""dsm_calib_temp_0""
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register "dsm_param_file_name" = ""dsm_param""
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register "vmon_slot_no" = "0"
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register "imon_slot_no" = "1"
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device i2c 0x38 on
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device i2c 0x38 on
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end
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end
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end
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end
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@ -133,6 +136,9 @@ chip soc/intel/alderlake
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register "name" = ""MXW1""
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register "name" = ""MXW1""
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register "r0_calib_key" = ""dsm_calib_r0_1""
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register "r0_calib_key" = ""dsm_calib_r0_1""
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register "temperature_calib_key" = ""dsm_calib_temp_1""
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register "temperature_calib_key" = ""dsm_calib_temp_1""
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register "dsm_param_file_name" = ""dsm_param""
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register "vmon_slot_no" = "1"
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register "imon_slot_no" = "0"
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device i2c 0x3c on
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device i2c 0x3c on
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end
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end
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end
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end
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