mb/google/brya/variants/gimble: Update audio setting

Add vmon-slot-no,imon-slot-no and dsm_param_file_name in overridetree.cb

BUG=b:197701952
TEST=build and check SSDT

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ie646360c4ebbf25762b374c5bc3ef2017989fb2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57832
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Mark Hsieh 2021-09-22 20:50:33 +08:00 committed by Felix Held
parent b0d87f753c
commit 3673a16546
1 changed files with 6 additions and 0 deletions

View File

@ -124,6 +124,9 @@ chip soc/intel/alderlake
register "name" = ""MXW0"" register "name" = ""MXW0""
register "r0_calib_key" = ""dsm_calib_r0_0"" register "r0_calib_key" = ""dsm_calib_r0_0""
register "temperature_calib_key" = ""dsm_calib_temp_0"" register "temperature_calib_key" = ""dsm_calib_temp_0""
register "dsm_param_file_name" = ""dsm_param""
register "vmon_slot_no" = "0"
register "imon_slot_no" = "1"
device i2c 0x38 on device i2c 0x38 on
end end
end end
@ -133,6 +136,9 @@ chip soc/intel/alderlake
register "name" = ""MXW1"" register "name" = ""MXW1""
register "r0_calib_key" = ""dsm_calib_r0_1"" register "r0_calib_key" = ""dsm_calib_r0_1""
register "temperature_calib_key" = ""dsm_calib_temp_1"" register "temperature_calib_key" = ""dsm_calib_temp_1""
register "dsm_param_file_name" = ""dsm_param""
register "vmon_slot_no" = "1"
register "imon_slot_no" = "0"
device i2c 0x3c on device i2c 0x3c on
end end
end end