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x86/mtrr: don't assume size of ROM cached during CAR mode 

Romstage and ramstage can use 2 different values for the
amount of ROM to cache just under 4GiB in the address
space. Don't assume a cpu's romstage caching policy
for the ROM.

Change-Id: I689fdf4d1f78e9556b0bc258e05c7b9bb99c48e1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4846
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Aaron Durbin 2014-01-27 16:39:17 -06:00 committed by Aaron Durbin
parent e6767674af
commit 3674ccfa3e
1 changed files with 0 additions and 4 deletions
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4
src/include/cpu/x86/mtrr.h
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@ -134,10 +134,6 @@ void set_var_mtrr(unsigned reg, unsigned base, unsigned size, unsigned type);
#define CACHE_ROM_BASE (((1<<20) - (CACHE_ROM_SIZE>>12))<<12)
#if ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) * 1UL > CACHE_ROM_BASE * 1UL)
# error "CAR region (WB) and flash (WP) regions overlap."
#endif
#if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0
# error "CONFIG_RAMTOP must be a power of 2"
#endif