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mainboard/google/reef: add new memory SKUs 

Two new SKUs are being utilized for reef DVT. Add the following:
Hynix 8GiB using H9HCNNNBPUMLHR-NLE -- id: 4'b0100
Hynix 4GIB using H9HCNNN8KUMLHR-NLE -- id: 4'b0101

BUG=chrome-os-partner:56738

Change-Id: I39ed9e827501939b92cbcce6092302b5a23d1d78
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16374
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Aaron Durbin 2016-08-30 16:57:37 -05:00
parent 0577a1e9d3
commit 3681de8ab6
1 changed files with 20 additions and 0 deletions
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20
src/mainboard/google/reef/romstage.c
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@ -113,6 +113,26 @@ static const struct lpddr4_sku skus[] = {
.part_num = "MT53B256M32D1NP", .part_num = "MT53B256M32D1NP",
.disable_periodic_retraining = 1, .disable_periodic_retraining = 1,
}, },
/*
* H9HCNNNBPUMLHR-NLE - both logical channels. While the parts
* are listed at 16Gb there are 2 ranks per channel so indicate the
* density as 8Gb per rank.
*/
[4] = {
.speed = LP4_SPEED_2400,
.ch0_rank_density = LP4_8Gb_DENSITY,
.ch1_rank_density = LP4_8Gb_DENSITY,
.ch0_dual_rank = 1,
.ch1_dual_rank = 1,
.part_num = "H9HCNNNBPUMLHR",
},
/* H9HCNNN8KUMLHR-NLE - both logical channels */
[5] = {
.speed = LP4_SPEED_2400,
.ch0_rank_density = LP4_8Gb_DENSITY,
.ch1_rank_density = LP4_8Gb_DENSITY,
.part_num = "H9HCNNN8KUMLHR",
},
/* K4F8E304HB-MGCH - both logical channels */ /* K4F8E304HB-MGCH - both logical channels */
[PROTO_SKU] = { [PROTO_SKU] = {
.speed = LP4_SPEED_2400, .speed = LP4_SPEED_2400,