mainboard: Add ASRock H81M-HDS
Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.5 with kernel 4.9. This board works quite well under coreboot. A list of what works and what doesn't can be found in the documentation part of this commit. The file `data.vbt` matches the VBT in the latest stable version of the vendor firmware (version 2.20). Change-Id: I53483bb9fa335e86e85dfc487fef03fce4b85e2a Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/29390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Tristan Corrick
Patrick Georgi
parent
b2632cec0e
commit
3693294112
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@ -0,0 +1,146 @@
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# ASRock H81M-HDS
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This page describes how to run coreboot on the [ASRock H81M-HDS].
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## Required proprietary blobs
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This board currently requires a proprietary blob in order to initialise
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the RAM and a few other components. The blob largely consists of Intel's
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Memory Reference Code (shortened to mrc), and is just under 200 KiB
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in size. It is also known as a system agent binary. Unfortunately,
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it is not currently possible to distribute this as part of coreboot.
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However, the mrc can be obtained from a Haswell Chromebook firmware
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image, and you might find one online. The mrc from a ChromeOS image can
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be extracted with the following command. If extracting from a "standard"
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coreboot image, omit `-r RO_SECTION`.
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```bash
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cbfstool coreboot.rom extract -f mrc.bin -n mrc.bin -r RO_SECTION
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```
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Now, place mrc.bin in the root of the coreboot directory.
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Alternatively, place it anywhere you want, and set `MRC_FILE` to its
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location when building coreboot.
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## Building coreboot
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A fully working image should be possible just by setting your MAC
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address and obtaining the Haswell mrc. You can set the basic config
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with the following commands. However, it is strongly advised to use
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`make menuconfig` afterwards (or instead), so that you can see all of
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the settings.
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```bash
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make distclean # Note: this will remove your current config, if it exists.
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touch .config
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./util/scripts/config --enable VENDOR_ASROCK
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./util/scripts/config --enable BOARD_ASROCK_H81M_HDS
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./util/scripts/config --enable HAVE_MRC
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./util/scripts/config --set-str REALTEK_8168_MACADDRESS "xx:xx:xx:xx:xx:xx" # Fill this in!
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make olddefconfig
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```
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If you don't plan on using coreboot's serial console to collect logs,
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you might want to disable it at this point (`./util/scripts/config
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--disable CONSOLE_SERIAL`). It should reduce the boot time by several
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seconds. However, a more flexible method is to change the console log
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level from within an OS using `util/nvramtool`, or with the `nvramcui`
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payload.
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Now, run `make` to build the coreboot image.
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## Flashing coreboot
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### Internal programming
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The main SPI flash can be accessed using [flashrom]. By default, only
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the BIOS region of the flash is writable. If you wish to change any
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other region, such as the Management Engine or firmware descriptor, then
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an external programmer is required (unless you find a clever way around
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the flash protection).
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The following command may be used to flash coreboot:
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```bash
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sudo flashrom -p internal --ifd -i bios --noverify-all -w coreboot.rom
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```
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The use of `--noverify-all` is required since the Management Engine
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region is not readable even by the host.
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### External programming
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The flash chip is a 4 MiB socketed DIP-8 chip. Specifically, it's a
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Winbond W25Q32FV, whose datasheet can be found [here][W25Q32FV].
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The chip is located to the bottom right-hand side of the board. For
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a precise location, refer to section 1.4 (Motherboard Layout) of the
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[board manual], where the chip is labelled "32Mb BIOS". Take note of
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the chip's orientation, remove it from its socket, and flash it with
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an external programmer. For reference, the notch in the chip should be
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facing towards the bottom of the board.
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## Known issues
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- PCIe graphics is non-functional. The PCIe 16x slot doesn't work
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with other devices, either.
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- The VGA port doesn't work until the OS reinitialises the display.
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- There is no automatic, OS-independent fan control. This is because
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the super I/O hardware monitor can only obtain valid CPU temperature
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readings from the PECI agent, but the required driver doesn't exist
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in coreboot. The `coretemp` driver can still be used for accurate CPU
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temperature readings from an OS.
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## Untested
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- parallel port
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- PS/2 keyboard
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- EHCI debug
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- TPM
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- infrared module
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- chassis intrusion header
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- chassis speaker header
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## Working
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- USB
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- S3 suspend/resume
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- Gigabit Ethernet
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- integrated graphics
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- PCIe (but not the 16x slot, see [Known issues](#known-issues))
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- SATA
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- PS/2 mouse
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- serial port
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- hardware monitor (see [Known issues](#known-issues))
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- onboard audio
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- front panel audio
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- initialisation with Haswell mrc version 1.6.1 build 2
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- graphics init with libgfxinit (see [Known issues](#known-issues))
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- flashrom under the vendor firmware
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- flashrom under coreboot
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- Wake-on-LAN
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- Using `me_cleaner`
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## Technology
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```eval_rst
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+------------------+--------------------------------------------------+
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| Northbridge | Intel Haswell |
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+------------------+--------------------------------------------------+
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| Southbridge | Intel Lynx Point (H81) |
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+------------------+--------------------------------------------------+
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| CPU | Intel Haswell (LGA1150) |
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+------------------+--------------------------------------------------+
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| Super I/O | Nuvoton NCT6776 |
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+------------------+--------------------------------------------------+
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| EC | None |
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+------------------+--------------------------------------------------+
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| Coprocessor | Intel Management Engine |
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+------------------+--------------------------------------------------+
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```
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[ASRock H81M-HDS]: https://www.asrock.com/mb/Intel/H81M-HDS/
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[W25Q32FV]: https://www.winbond.com/resource-files/w25q32fv%20revi%2010202015.pdf
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[flashrom]: https://flashrom.org/Flashrom
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[Board manual]: http://asrock.pc.cdn.bitgravity.com/Manual/H81M-HDS.pdf
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@ -6,6 +6,10 @@ This section contains documentation about coreboot on specific mainboards.
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- [P8H61-M LX](asus/p8h61-m_lx.md)
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## ASRock
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- [H81M-HDS](asrock/h81m-hds.md)
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## Cavium
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- [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)
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@ -0,0 +1,89 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
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##
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## This program is free software: you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation, either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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if BOARD_ASROCK_H81M_HDS
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_4096
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select CPU_INTEL_HASWELL
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select HAVE_CMOS_DEFAULT
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select HAVE_SMI_HANDLER
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select INTEL_GMA_HAVE_VBT
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select INTEL_INT15
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select MAINBOARD_HAS_LIBGFXINIT
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select NORTHBRIDGE_INTEL_HASWELL
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select REALTEK_8168_RESET
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select RT8168_SET_LED_MODE
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select SERIRQ_CONTINUOUS_MODE
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select SOUTHBRIDGE_INTEL_LYNXPOINT
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select SUPERIO_NUVOTON_NCT6776
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select SUPERIO_NUVOTON_NCT6776_COM_A
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select TSC_MONOTONIC_TIMER
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config CBFS_SIZE
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hex
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default 0x200000
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#
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# The override of GFX_GMA_CPU_VARIANT should be removed once the patches
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# for dynamic CPU detection are merged in libgfxinit.
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#
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config GFX_GMA_CPU_VARIANT
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string
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default "Normal"
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config MAINBOARD_DIR
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string
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default asrock/h81m-hds
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config MAINBOARD_PART_NUMBER
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string
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default "H81M-HDS"
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config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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hex
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default 0x8c5c
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config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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hex
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default 0x1849
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# This is overridden if CMOS is used for configuration values.
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config MAINBOARD_POWER_ON_AFTER_POWER_FAIL
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bool
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default n
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config MAX_CPUS
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int
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default 8
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config MMCONF_BASE_ADDRESS
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hex
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default 0xf0000000
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#
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# Since this is a desktop board, the assumption is made that most users
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# would want CMOS configuration enabled by default.
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#
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config USE_OPTION_TABLE
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bool
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default y
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endif
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@ -0,0 +1,2 @@
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config BOARD_ASROCK_H81M_HDS
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bool "H81M-HDS"
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@ -0,0 +1,17 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
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##
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## This program is free software: you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation, either version 2 of the License, or
|
||||
## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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@ -0,0 +1,24 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Tristan Corrick <tristan@corrick.kiwi>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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||||
*
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||||
* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Method(_WAK, 1)
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{
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Return (Package() { 0, 0 })
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}
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Method(_PTS, 1)
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{
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}
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@ -0,0 +1,26 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
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*
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* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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||||
* GNU General Public License for more details.
|
||||
*/
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||||
|
||||
#define SUPERIO_DEV SIO0
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#define SUPERIO_PNP_BASE 0x2e
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#define NCT6776_SHOW_PP
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#define NCT6776_SHOW_SP1
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#define NCT6776_SHOW_KBC
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#define NCT6776_SHOW_HWM
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#undef NCT6776_SHOW_GPIO
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#include <superio/nuvoton/nct6776/acpi/superio.asl>
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
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*
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* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
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*/
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#include <southbridge/intel/lynxpoint/nvs.h>
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void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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}
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@ -0,0 +1,7 @@
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Category: desktop
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Board URL: https://www.asrock.com/mb/Intel/H81M-HDS/
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ROM package: DIP-8
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ROM protocol: SPI
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ROM socketed: y
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Flashrom support: y
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Release year: 2013
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@ -0,0 +1,4 @@
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boot_option=Fallback
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debug_level=Debug
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nmi=Enable
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power_on_after_fail=Disable
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@ -0,0 +1,90 @@
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##
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## This file is part of the coreboot project.
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||||
##
|
||||
## Copyright (C) 2007-2008 coresystems GmbH
|
||||
## Copyright (C) 2014 Vladimir Serbinenko
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
entries
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register A
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register B
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register C
|
||||
#96 4 r 0 status_c_rsvd
|
||||
#100 1 r 0 uf_flag
|
||||
#101 1 r 0 af_flag
|
||||
#102 1 r 0 pf_flag
|
||||
#103 1 r 0 irqf_flag
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register D
|
||||
#104 7 r 0 status_d_rsvd
|
||||
#111 1 r 0 valid_cmos_ram
|
||||
# -----------------------------------------------------------------
|
||||
# Diagnostic Status Register
|
||||
#112 8 r 0 diag_rsvd1
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
0 120 r 0 reserved_memory
|
||||
#120 264 r 0 unused
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||
384 1 e 3 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# coreboot config options: console
|
||||
#392 3 r 0 unused
|
||||
395 4 e 4 debug_level
|
||||
#399 1 r 0 unused
|
||||
|
||||
#400 8 r 0 reserved for century byte
|
||||
|
||||
# coreboot config options: southbridge
|
||||
408 1 e 1 nmi
|
||||
409 2 e 1 power_on_after_fail
|
||||
|
||||
# coreboot config options: check sums
|
||||
984 16 h 0 check_sum
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
|
||||
3 0 Fallback
|
||||
3 1 Normal
|
||||
|
||||
4 0 Emergency
|
||||
4 1 Alert
|
||||
4 2 Critical
|
||||
4 3 Error
|
||||
4 4 Warning
|
||||
4 5 Notice
|
||||
4 6 Info
|
||||
4 7 Debug
|
||||
4 8 Spew
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
checksum 392 415 984
|
||||
Binary file not shown.
|
|
@ -0,0 +1,173 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
|
||||
##
|
||||
## This program is free software: you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation, either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
chip northbridge/intel/haswell
|
||||
register "gpu_ddi_e_connected" = "1"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/intel/haswell
|
||||
register "c1_acpower" = "1"
|
||||
register "c1_battery" = "1"
|
||||
register "c2_acpower" = "3"
|
||||
register "c2_battery" = "3"
|
||||
register "c3_acpower" = "5"
|
||||
register "c3_battery" = "5"
|
||||
|
||||
device lapic 0 on end
|
||||
device lapic 0xacac off end
|
||||
end
|
||||
end
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on # Host bridge
|
||||
subsystemid 0x1849 0x0c00
|
||||
end
|
||||
|
||||
device pci 01.0 on # PCIe graphics
|
||||
subsystemid 0x1849 0x0c01
|
||||
end
|
||||
|
||||
device pci 02.0 on # VGA controller
|
||||
subsystemid 0x1849 0x0402
|
||||
end
|
||||
|
||||
device pci 03.0 on # Mini-HD audio
|
||||
subsystemid 0x1849 0x0c0c
|
||||
end
|
||||
|
||||
chip southbridge/intel/lynxpoint
|
||||
register "pirqa_routing" = "0x8b"
|
||||
register "pirqb_routing" = "0x80"
|
||||
register "pirqc_routing" = "0x8b"
|
||||
register "pirqd_routing" = "0x8a"
|
||||
register "pirqe_routing" = "0x80"
|
||||
register "pirqf_routing" = "0x80"
|
||||
register "pirqg_routing" = "0x80"
|
||||
register "pirqh_routing" = "0x8a"
|
||||
|
||||
register "sata_ahci" = "1"
|
||||
register "sata_port_map" = "0x33"
|
||||
|
||||
register "gen1_dec" = "0x00000295" # Super I/O HWM
|
||||
|
||||
device pci 14.0 on # xHCI controller
|
||||
subsystemid 0x1849 0x8c31
|
||||
end
|
||||
device pci 16.0 on # Management Engine interface 1
|
||||
subsystemid 0x1849 0x8c3a
|
||||
end
|
||||
device pci 16.1 off end # Management Engine interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT
|
||||
device pci 19.0 off end # Intel Gigabit Ethernet
|
||||
device pci 1a.0 on # EHCI controller #2
|
||||
subsystemid 0x1849 0x8c2d
|
||||
end
|
||||
device pci 1b.0 on # HD audio controller
|
||||
subsystemid 0x1849 0x7662
|
||||
end
|
||||
device pci 1c.0 on # PCIe port #1
|
||||
subsystemid 0x1849 0x8c10
|
||||
end
|
||||
device pci 1c.1 off end # PCIe port #2
|
||||
device pci 1c.2 off end # PCIe port #3
|
||||
device pci 1c.3 on # Realtek Gigabit Ethernet
|
||||
subsystemid 0x1849 0x8c16
|
||||
chip drivers/net
|
||||
register "customized_leds" = "0x0824"
|
||||
device pci 00.0 on
|
||||
subsystemid 0x1849 0x8168
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 1c.4 on # ASMedia USB controller
|
||||
subsystemid 0x1849 0x8c18
|
||||
device pci 00.0 on
|
||||
subsystemid 0x1849 0x1042
|
||||
end
|
||||
end
|
||||
device pci 1c.5 on # PCIe 1x slot
|
||||
subsystemid 0x1849 0x8c1a
|
||||
end
|
||||
device pci 1c.6 off end # PCIe port #7
|
||||
device pci 1c.7 off end # PCIe port #8
|
||||
device pci 1d.0 on # EHCI controller #1
|
||||
subsystemid 0x1849 0x8c26
|
||||
end
|
||||
device pci 1f.0 on # LPC bridge
|
||||
subsystemid 0x1849 0x8c5c
|
||||
|
||||
chip superio/nuvoton/nct6776
|
||||
device pnp 2e.0 off end # Floppy
|
||||
device pnp 2e.1 on # Parallel
|
||||
io 0x60 = 0x0378
|
||||
irq 0x70 = 7
|
||||
drq 0x74 = 4 # No DMA
|
||||
irq 0xf0 = 0x3c # Printer mode
|
||||
end
|
||||
device pnp 2e.2 on # UART A
|
||||
io 0x60 = 0x03f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 on # IR
|
||||
io 0x60 = 0x02f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.5 on # PS/2 KBC
|
||||
io 0x60 = 0x0060
|
||||
io 0x62 = 0x0064
|
||||
irq 0x70 = 1 # Keyboard
|
||||
irq 0x72 = 12 # Mouse
|
||||
end
|
||||
device pnp 2e.6 off end # CIR
|
||||
device pnp 2e.7 off end # GPIO8
|
||||
device pnp 2e.107 off end # GPIO9
|
||||
device pnp 2e.8 off end # WDT
|
||||
device pnp 2e.108 off end # GPIO0
|
||||
device pnp 2e.208 off end # GPIOA
|
||||
device pnp 2e.308 off end # GPIO base
|
||||
device pnp 2e.109 off end # GPIO1
|
||||
device pnp 2e.209 off end # GPIO2
|
||||
device pnp 2e.309 off end # GPIO3
|
||||
device pnp 2e.409 off end # GPIO4
|
||||
device pnp 2e.509 off end # GPIO5
|
||||
device pnp 2e.609 off end # GPIO6
|
||||
device pnp 2e.709 off end # GPIO7
|
||||
device pnp 2e.a off end # ACPI
|
||||
device pnp 2e.b on # HWM, LED
|
||||
io 0x60 = 0x0290
|
||||
io 0x62 = 0
|
||||
irq 0x70 = 0
|
||||
end
|
||||
device pnp 2e.d off end # VID
|
||||
device pnp 2e.e off end # CIR wake-up
|
||||
device pnp 2e.f off end # GPIO PP/OD
|
||||
device pnp 2e.14 off end # SVID
|
||||
device pnp 2e.16 off end # Deep sleep
|
||||
device pnp 2e.17 off end # GPIOA
|
||||
end
|
||||
end
|
||||
device pci 1f.2 on # SATA controller 1
|
||||
subsystemid 0x1849 0x8c02
|
||||
end
|
||||
device pci 1f.3 on # SMBus
|
||||
subsystemid 0x1849 0x8c22
|
||||
end
|
||||
device pci 1f.5 off end # SATA controller 2
|
||||
device pci 1f.6 off end # Thermal
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
|
||||
*
|
||||
* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
0x03, /* DSDT Revision: ACPI v3.0 */
|
||||
"COREv4", /* OEM ID */
|
||||
"COREBOOT", /* OEM Table ID */
|
||||
0x20181031 /* OEM Revision */
|
||||
)
|
||||
{
|
||||
#include "acpi/platform.asl"
|
||||
#include <southbridge/intel/lynxpoint/acpi/platform.asl>
|
||||
#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
|
||||
#include <southbridge/intel/lynxpoint/acpi/sleepstates.asl>
|
||||
#include <cpu/intel/haswell/acpi/cpu.asl>
|
||||
|
||||
Scope (\_SB)
|
||||
{
|
||||
Device (PCI0)
|
||||
{
|
||||
#include <northbridge/intel/haswell/acpi/haswell.asl>
|
||||
#include <southbridge/intel/lynxpoint/acpi/pch.asl>
|
||||
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
--
|
||||
-- This file is part of the coreboot project.
|
||||
--
|
||||
-- Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
|
||||
with HW.GFX.GMA;
|
||||
with HW.GFX.GMA.Display_Probing;
|
||||
|
||||
use HW.GFX.GMA;
|
||||
use HW.GFX.GMA.Display_Probing;
|
||||
|
||||
private package GMA.Mainboard is
|
||||
|
||||
ports : constant Port_List :=
|
||||
(HDMI1,
|
||||
HDMI3,
|
||||
Analog,
|
||||
others => Disabled);
|
||||
|
||||
end GMA.Mainboard;
|
||||
|
|
@ -0,0 +1,168 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
|
||||
*
|
||||
* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef ASROCK_H81M_HDS_GPIO_H
|
||||
#define ASROCK_H81M_HDS_GPIO_H
|
||||
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
.gpio0 = GPIO_MODE_GPIO,
|
||||
.gpio1 = GPIO_MODE_GPIO,
|
||||
.gpio6 = GPIO_MODE_GPIO,
|
||||
.gpio7 = GPIO_MODE_GPIO,
|
||||
.gpio12 = GPIO_MODE_GPIO,
|
||||
.gpio13 = GPIO_MODE_GPIO,
|
||||
.gpio14 = GPIO_MODE_GPIO,
|
||||
.gpio15 = GPIO_MODE_GPIO,
|
||||
.gpio16 = GPIO_MODE_GPIO,
|
||||
.gpio17 = GPIO_MODE_GPIO,
|
||||
.gpio24 = GPIO_MODE_GPIO,
|
||||
.gpio27 = GPIO_MODE_GPIO,
|
||||
.gpio28 = GPIO_MODE_GPIO,
|
||||
.gpio31 = GPIO_MODE_GPIO,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
.gpio0 = GPIO_DIR_INPUT,
|
||||
.gpio1 = GPIO_DIR_INPUT,
|
||||
.gpio6 = GPIO_DIR_INPUT,
|
||||
.gpio7 = GPIO_DIR_INPUT,
|
||||
.gpio12 = GPIO_DIR_OUTPUT,
|
||||
.gpio13 = GPIO_DIR_INPUT,
|
||||
.gpio14 = GPIO_DIR_OUTPUT,
|
||||
.gpio15 = GPIO_DIR_OUTPUT,
|
||||
.gpio16 = GPIO_DIR_INPUT,
|
||||
.gpio17 = GPIO_DIR_INPUT,
|
||||
.gpio24 = GPIO_DIR_OUTPUT,
|
||||
.gpio27 = GPIO_DIR_INPUT,
|
||||
.gpio28 = GPIO_DIR_OUTPUT,
|
||||
.gpio31 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
.gpio12 = GPIO_LEVEL_HIGH,
|
||||
.gpio14 = GPIO_LEVEL_LOW,
|
||||
.gpio15 = GPIO_LEVEL_LOW,
|
||||
.gpio24 = GPIO_LEVEL_LOW,
|
||||
.gpio28 = GPIO_LEVEL_LOW,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_reset = {
|
||||
.gpio8 = GPIO_RESET_RSMRST,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
.gpio13 = GPIO_INVERT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
.gpio32 = GPIO_MODE_GPIO,
|
||||
.gpio33 = GPIO_MODE_GPIO,
|
||||
.gpio34 = GPIO_MODE_GPIO,
|
||||
.gpio35 = GPIO_MODE_GPIO,
|
||||
.gpio42 = GPIO_MODE_GPIO,
|
||||
.gpio43 = GPIO_MODE_GPIO,
|
||||
.gpio46 = GPIO_MODE_GPIO,
|
||||
.gpio49 = GPIO_MODE_GPIO,
|
||||
.gpio50 = GPIO_MODE_GPIO,
|
||||
.gpio51 = GPIO_MODE_GPIO,
|
||||
.gpio52 = GPIO_MODE_GPIO,
|
||||
.gpio53 = GPIO_MODE_GPIO,
|
||||
.gpio54 = GPIO_MODE_GPIO,
|
||||
.gpio55 = GPIO_MODE_GPIO,
|
||||
.gpio57 = GPIO_MODE_GPIO,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
.gpio32 = GPIO_DIR_OUTPUT,
|
||||
.gpio33 = GPIO_DIR_OUTPUT,
|
||||
.gpio34 = GPIO_DIR_INPUT,
|
||||
.gpio35 = GPIO_DIR_OUTPUT,
|
||||
.gpio42 = GPIO_DIR_OUTPUT,
|
||||
.gpio43 = GPIO_DIR_OUTPUT,
|
||||
.gpio46 = GPIO_DIR_INPUT,
|
||||
.gpio49 = GPIO_DIR_INPUT,
|
||||
.gpio50 = GPIO_DIR_INPUT,
|
||||
.gpio51 = GPIO_DIR_OUTPUT,
|
||||
.gpio52 = GPIO_DIR_INPUT,
|
||||
.gpio53 = GPIO_DIR_OUTPUT,
|
||||
.gpio54 = GPIO_DIR_INPUT,
|
||||
.gpio55 = GPIO_DIR_OUTPUT,
|
||||
.gpio57 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
.gpio32 = GPIO_LEVEL_HIGH,
|
||||
.gpio33 = GPIO_LEVEL_HIGH,
|
||||
.gpio35 = GPIO_LEVEL_LOW,
|
||||
.gpio42 = GPIO_LEVEL_LOW,
|
||||
.gpio43 = GPIO_LEVEL_LOW,
|
||||
.gpio51 = GPIO_LEVEL_HIGH,
|
||||
.gpio53 = GPIO_LEVEL_HIGH,
|
||||
.gpio55 = GPIO_LEVEL_HIGH,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_reset = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
.gpio68 = GPIO_MODE_GPIO,
|
||||
.gpio69 = GPIO_MODE_GPIO,
|
||||
.gpio72 = GPIO_MODE_GPIO,
|
||||
.gpio73 = GPIO_MODE_GPIO,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
.gpio68 = GPIO_DIR_INPUT,
|
||||
.gpio69 = GPIO_DIR_INPUT,
|
||||
.gpio72 = GPIO_DIR_INPUT,
|
||||
.gpio73 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
||||
};
|
||||
|
||||
const struct pch_gpio_map mainboard_gpio_map = {
|
||||
.set1 = {
|
||||
.mode = &pch_gpio_set1_mode,
|
||||
.direction = &pch_gpio_set1_direction,
|
||||
.level = &pch_gpio_set1_level,
|
||||
.blink = &pch_gpio_set1_blink,
|
||||
.invert = &pch_gpio_set1_invert,
|
||||
.reset = &pch_gpio_set1_reset,
|
||||
},
|
||||
.set2 = {
|
||||
.mode = &pch_gpio_set2_mode,
|
||||
.direction = &pch_gpio_set2_direction,
|
||||
.level = &pch_gpio_set2_level,
|
||||
.reset = &pch_gpio_set2_reset,
|
||||
},
|
||||
.set3 = {
|
||||
.mode = &pch_gpio_set3_mode,
|
||||
.direction = &pch_gpio_set3_direction,
|
||||
.level = &pch_gpio_set3_level,
|
||||
.reset = &pch_gpio_set3_reset,
|
||||
},
|
||||
};
|
||||
|
||||
#endif /* ASROCK_H81M_HDS_GPIO_H */
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
|
||||
*
|
||||
* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
0x10ec0662, /* Realtek ALC662 rev1 */
|
||||
0x18497662, /* Subsystem ID */
|
||||
11, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(1, 0x18497662),
|
||||
AZALIA_PIN_CFG(1, 0x14, 0x01014010),
|
||||
AZALIA_PIN_CFG(1, 0x15, 0x40000000),
|
||||
AZALIA_PIN_CFG(1, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(1, 0x18, 0x01a19040),
|
||||
AZALIA_PIN_CFG(1, 0x19, 0x02a19050),
|
||||
AZALIA_PIN_CFG(1, 0x1a, 0x0181304f),
|
||||
AZALIA_PIN_CFG(1, 0x1b, 0x02214020),
|
||||
AZALIA_PIN_CFG(1, 0x1c, 0x411111f0),
|
||||
AZALIA_PIN_CFG(1, 0x1d, 0x40a4c601),
|
||||
AZALIA_PIN_CFG(1, 0x1e, 0x411111f0),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
|
||||
*
|
||||
* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/device.h>
|
||||
#include <drivers/intel/gma/int15.h>
|
||||
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
|
||||
GMA_INT15_PANEL_FIT_DEFAULT,
|
||||
GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
|
@ -0,0 +1,131 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2010 coresystems GmbH
|
||||
* Copyright (C) 2012 Google Inc.
|
||||
* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <cpu/intel/romstage.h>
|
||||
#include <cpu/intel/haswell/haswell.h>
|
||||
#include <northbridge/intel/haswell/haswell.h>
|
||||
#include <northbridge/intel/haswell/pei_data.h>
|
||||
#include <southbridge/intel/lynxpoint/pch.h>
|
||||
#include <superio/nuvoton/common/nuvoton.h>
|
||||
#include <superio/nuvoton/nct6776/nct6776.h>
|
||||
#include "gpio.h"
|
||||
|
||||
static const struct rcba_config_instruction rcba_config[] = {
|
||||
RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)),
|
||||
RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)),
|
||||
RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),
|
||||
RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)),
|
||||
RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)),
|
||||
RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)),
|
||||
RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB)),
|
||||
RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),
|
||||
|
||||
RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),
|
||||
|
||||
RCBA_END_CONFIG,
|
||||
};
|
||||
|
||||
void mainboard_config_superio(void)
|
||||
{
|
||||
const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0);
|
||||
const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1);
|
||||
const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI);
|
||||
const pnp_devfn_t IR_DEV = PNP_DEV(0x2e, NCT6776_SP2);
|
||||
|
||||
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
|
||||
nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV);
|
||||
|
||||
/* Select HWM/LED functions instead of floppy functions. */
|
||||
pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03);
|
||||
pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24);
|
||||
|
||||
/* Power RAM in S3 and let the PCH handle power failure actions. */
|
||||
pnp_set_logical_device(ACPI_DEV);
|
||||
pnp_write_config(ACPI_DEV, 0xe4, 0x70);
|
||||
|
||||
/*
|
||||
* Don't know what's needed here, just set the same as the vendor
|
||||
* firmware.
|
||||
*/
|
||||
pnp_set_logical_device(IR_DEV);
|
||||
pnp_write_config(IR_DEV, 0xf1, 0x5c);
|
||||
|
||||
nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV);
|
||||
}
|
||||
|
||||
void mainboard_romstage_entry(unsigned long bist)
|
||||
{
|
||||
struct pei_data pei_data = {
|
||||
.pei_version = PEI_VERSION,
|
||||
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
|
||||
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
|
||||
.epbar = DEFAULT_EPBAR,
|
||||
.pciexbar = DEFAULT_PCIEXBAR,
|
||||
.smbusbar = SMBUS_IO_BASE,
|
||||
.wdbbar = 0x4000000,
|
||||
.wdbsize = 0x1000,
|
||||
.hpet_address = HPET_ADDR,
|
||||
.rcba = (uintptr_t)DEFAULT_RCBA,
|
||||
.pmbase = DEFAULT_PMBASE,
|
||||
.gpiobase = DEFAULT_GPIOBASE,
|
||||
.temp_mmio_base = 0xfed08000,
|
||||
.system_type = 1, /* desktop/server */
|
||||
.tseg_size = CONFIG_SMM_TSEG_SIZE,
|
||||
.spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 },
|
||||
.ec_present = 0,
|
||||
.dimm_channel0_disabled = 2, /* Disable DIMM 1 on channel 0. */
|
||||
.dimm_channel1_disabled = 2, /* Disable DIMM 1 on channel 1. */
|
||||
.max_ddr3_freq = 1600,
|
||||
.usb2_ports = {
|
||||
/* Length, Enable, OCn#, Location */
|
||||
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
|
||||
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
|
||||
{ 0x0040, 1, 1, USB_PORT_BACK_PANEL },
|
||||
{ 0x0040, 1, 1, USB_PORT_BACK_PANEL },
|
||||
{ 0x0040, 1, 2, USB_PORT_BACK_PANEL },
|
||||
{ 0x0040, 1, 2, USB_PORT_BACK_PANEL },
|
||||
{ 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
|
||||
{ 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
|
||||
{ 0x0040, 1, 4, USB_PORT_BACK_PANEL },
|
||||
{ 0x0040, 1, 4, USB_PORT_BACK_PANEL },
|
||||
{ 0x0040, 1, 5, USB_PORT_BACK_PANEL },
|
||||
{ 0x0040, 1, 5, USB_PORT_BACK_PANEL },
|
||||
{ 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
|
||||
{ 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
|
||||
},
|
||||
.usb3_ports = {
|
||||
/* Enable, OCn# */
|
||||
{ 1, 0 },
|
||||
{ 1, 0 },
|
||||
{ 0, USB_OC_PIN_SKIP },
|
||||
{ 0, USB_OC_PIN_SKIP },
|
||||
{ 0, USB_OC_PIN_SKIP },
|
||||
{ 0, USB_OC_PIN_SKIP },
|
||||
},
|
||||
};
|
||||
|
||||
struct romstage_params romstage_params = {
|
||||
.pei_data = &pei_data,
|
||||
.gpio_map = &mainboard_gpio_map,
|
||||
.rcba_config = &rcba_config[0],
|
||||
.bist = bist,
|
||||
};
|
||||
|
||||
romstage_common(&romstage_params);
|
||||
}
|
||||
Loading…
Reference in New Issue