mediatek/mt8173: Enable 4GB mode

If the system is using 4GB of memory, enable 4GB mode in
the memory controller.

Change-Id: I4d0f8ad8d43ff45dd786f4244b11c0879d2088cd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 94c8b7ad911c93c4325113e7afc009f2f81d2275
Original-Change-Id: Ia3640882a46e695550e679dc70611855b64a560f
Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/331811
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14088
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
PH Hsu 2015-12-16 13:48:10 +08:00 committed by Martin Roth
parent 00feb3928f
commit 3693d0f94b
3 changed files with 26 additions and 0 deletions

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@ -25,6 +25,8 @@
#include <soc/dramc_pi_api.h> #include <soc/dramc_pi_api.h>
#include <soc/mt6391.h> #include <soc/mt6391.h>
#include <soc/pll.h> #include <soc/pll.h>
#include <soc/infracfg.h>
#include <soc/pericfg.h>
struct emi_regs *emi_regs = (void *)EMI_BASE; struct emi_regs *emi_regs = (void *)EMI_BASE;
@ -163,6 +165,17 @@ size_t sdram_size(void)
return ((size_t)1 << (bit_counter - 3)); return ((size_t)1 << (bit_counter - 3));
} }
static void init_4GB_mode(void)
{
if (sdram_size() == (size_t)4 * GiB) {
setbits_le32(&mt8173_pericfg->axi_bus_ctl3, PERISYS_4G_SUPPORT);
setbits_le32(&mt8173_infracfg->infra_misc, DDR_4GB_SUPPORT_EN);
} else {
clrbits_le32(&mt8173_pericfg->axi_bus_ctl3, PERISYS_4G_SUPPORT);
clrbits_le32(&mt8173_infracfg->infra_misc, DDR_4GB_SUPPORT_EN);
}
}
void mt_set_emi(const struct mt8173_sdram_params *sdram_params) void mt_set_emi(const struct mt8173_sdram_params *sdram_params)
{ {
/* voltage info */ /* voltage info */
@ -175,4 +188,5 @@ void mt_set_emi(const struct mt8173_sdram_params *sdram_params)
init_dram(sdram_params); init_dram(sdram_params);
do_calib(sdram_params); do_calib(sdram_params);
init_4GB_mode();
} }

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@ -118,4 +118,8 @@ enum {
L2C_SRAM_PDN = 1 << 7 L2C_SRAM_PDN = 1 << 7
}; };
enum {
DDR_4GB_SUPPORT_EN = 1 << 13
};
#endif /* __SOC_MEDIATEK_MT8173_INFRACFG_H__ */ #endif /* __SOC_MEDIATEK_MT8173_INFRACFG_H__ */

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@ -89,4 +89,12 @@ enum {
PERICFG_UART0_PDN = 1 << 19 PERICFG_UART0_PDN = 1 << 19
}; };
/*
* PERI 4GB control
*/
enum {
PERISYS_4G_SUPPORT = 1 << 15
};
#endif /* __SOC_MEDIATEK_MT8173_PERICFG_H__ */ #endif /* __SOC_MEDIATEK_MT8173_PERICFG_H__ */