mediatek/mt8173: Enable 4GB mode
If the system is using 4GB of memory, enable 4GB mode in the memory controller. Change-Id: I4d0f8ad8d43ff45dd786f4244b11c0879d2088cd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 94c8b7ad911c93c4325113e7afc009f2f81d2275 Original-Change-Id: Ia3640882a46e695550e679dc70611855b64a560f Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/331811 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14088 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@ -25,6 +25,8 @@
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#include <soc/dramc_pi_api.h>
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#include <soc/dramc_pi_api.h>
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#include <soc/mt6391.h>
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#include <soc/mt6391.h>
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#include <soc/pll.h>
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#include <soc/pll.h>
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#include <soc/infracfg.h>
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#include <soc/pericfg.h>
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struct emi_regs *emi_regs = (void *)EMI_BASE;
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struct emi_regs *emi_regs = (void *)EMI_BASE;
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@ -163,6 +165,17 @@ size_t sdram_size(void)
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return ((size_t)1 << (bit_counter - 3));
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return ((size_t)1 << (bit_counter - 3));
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}
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}
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static void init_4GB_mode(void)
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{
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if (sdram_size() == (size_t)4 * GiB) {
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setbits_le32(&mt8173_pericfg->axi_bus_ctl3, PERISYS_4G_SUPPORT);
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setbits_le32(&mt8173_infracfg->infra_misc, DDR_4GB_SUPPORT_EN);
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} else {
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clrbits_le32(&mt8173_pericfg->axi_bus_ctl3, PERISYS_4G_SUPPORT);
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clrbits_le32(&mt8173_infracfg->infra_misc, DDR_4GB_SUPPORT_EN);
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}
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}
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void mt_set_emi(const struct mt8173_sdram_params *sdram_params)
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void mt_set_emi(const struct mt8173_sdram_params *sdram_params)
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{
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{
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/* voltage info */
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/* voltage info */
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@ -175,4 +188,5 @@ void mt_set_emi(const struct mt8173_sdram_params *sdram_params)
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init_dram(sdram_params);
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init_dram(sdram_params);
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do_calib(sdram_params);
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do_calib(sdram_params);
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init_4GB_mode();
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}
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}
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@ -118,4 +118,8 @@ enum {
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L2C_SRAM_PDN = 1 << 7
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L2C_SRAM_PDN = 1 << 7
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};
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};
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enum {
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DDR_4GB_SUPPORT_EN = 1 << 13
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};
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#endif /* __SOC_MEDIATEK_MT8173_INFRACFG_H__ */
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#endif /* __SOC_MEDIATEK_MT8173_INFRACFG_H__ */
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@ -89,4 +89,12 @@ enum {
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PERICFG_UART0_PDN = 1 << 19
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PERICFG_UART0_PDN = 1 << 19
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};
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};
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/*
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* PERI 4GB control
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*/
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enum {
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PERISYS_4G_SUPPORT = 1 << 15
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};
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#endif /* __SOC_MEDIATEK_MT8173_PERICFG_H__ */
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#endif /* __SOC_MEDIATEK_MT8173_PERICFG_H__ */
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