google/oak: Add support for verstage
Add support for verstage [pg: split original commit into multiple commits] Change-Id: I8c9fe02f26bf8fa8381a7502a778bed300684986 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2827aa08ff8712c0245a22378f3ddb0ca054255d Original-Change-Id: I94a9ee2c00e25a37a92133f813d0cd11a3503656 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292662 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13052 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@ -24,10 +24,12 @@ config BOARD_SPECIFIC_OPTIONS
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select EC_GOOGLE_CHROMEEC_SPI
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select EC_GOOGLE_CHROMEEC_SPI
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select MAINBOARD_HAS_NATIVE_VGA_INIT
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select MAINBOARD_HAS_NATIVE_VGA_INIT
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select MAINBOARD_DO_NATIVE_VGA_INIT
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select MAINBOARD_DO_NATIVE_VGA_INIT
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select MAINBOARD_HAS_CHROMEOS
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config CHROMEOS
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config CHROMEOS
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select CHROMEOS_VBNV_EC
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select CHROMEOS_VBNV_EC
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select EC_SOFTWARE_SYNC
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select EC_SOFTWARE_SYNC
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select VBOOT2_MOCK_SECDATA
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select VIRTUAL_DEV_SWITCH
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select VIRTUAL_DEV_SWITCH
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config MAINBOARD_DIR
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config MAINBOARD_DIR
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@ -46,4 +48,12 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
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hex
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hex
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default 0
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default 0
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config DRIVER_TPM_I2C_BUS
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hex
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default 0x2
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config DRIVER_TPM_I2C_ADDR
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hex
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default 0x20
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endif # BOARD_GOOGLE_OAK
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endif # BOARD_GOOGLE_OAK
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@ -18,6 +18,9 @@ bootblock-y += memlayout.ld
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bootblock-y += chromeos.c
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bootblock-y += chromeos.c
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bootblock-y += boardid.c
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bootblock-y += boardid.c
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verstage-y += chromeos.c
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verstage-y += memlayout.ld
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romstage-y += chromeos.c
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romstage-y += chromeos.c
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romstage-y += romstage.c
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romstage-y += romstage.c
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romstage-y += memlayout.ld
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romstage-y += memlayout.ld
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