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mb/google/dedede/var/beadrix: Update PCIe and SATA pins for low power consumption 

To achieve low power consumption, we disable unused PCIe and SATA
pins at beadrix/overridetree.cb according to baseboard/devicetree.cb
and mainboard schematic. Original measured beadrix board's power
consumption is about 250 mW. After we disable unused PCIe and SATA
pins, as well as, enable the other low power MUX CL (3487086: USB
MUX: Update low power mode of MUX anx7447 used as MUX only |
https://chromium-review.googlesource.com/c/chromiumos/platform/ec/
+/3487086), the measured power consumption achieves about 110 ~ 116
mW, as well as, meets Google battery life for 14 days in the suspend
state and Intel low power consumption about 116 mW.

BRANCH=dedede
BUG=b:204882915
TEST=on beadrix, measured power consumption meets Intel power
consumption.

Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: I79ec524c5ce8f2a79da4aeba084786fb9dac17af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62776
Reviewed-by: Teddy Shih <teddyshihau@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Teddy Shih 2022-03-14 14:40:08 +08:00 committed by Karthik Ramasubramanian
parent 0fd3c38d84
commit 369b9ad787
1 changed files with 5 additions and 0 deletions
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5
src/mainboard/google/dedede/variants/beadrix/overridetree.cb
View File

@ -1,7 +1,9 @@
chip soc/intel/jasperlake chip soc/intel/jasperlake
# USB Port Configuration # USB Port Configuration
register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable unused USB2P_5 and USB2N_5
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera
register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable unused USB2P_7 and USB2N_7
# Intel Common SoC Config # Intel Common SoC Config
#+-------------------+---------------------------+ #+-------------------+---------------------------+
@ -115,6 +117,7 @@ chip soc/intel/jasperlake
device i2c 15 on end device i2c 15 on end
end end
end # I2C 0 end # I2C 0
device pci 17.0 off end # SATA. Baseboard/devicetree.cb is off
device pci 19.0 on device pci 19.0 on
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""10EC5682"" register "hid" = ""10EC5682""
@ -128,6 +131,8 @@ chip soc/intel/jasperlake
device i2c 1a on end device i2c 1a on end
end end
end # I2C 4 end # I2C 4
device pci 1c.6 off end # PCI Express Root Port 7 / SATA_0. Baseboard/devicetree.cb is off
device pci 1c.7 off end # PCI Express Root Port 8 / SATA_1
device pci 1f.3 on device pci 1f.3 on
chip drivers/generic/max98357a chip drivers/generic/max98357a
register "hid" = ""MX98360A"" register "hid" = ""MX98360A""