GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

gizmosphere/gizmo: Move support of SPD data in CBFS 

This code is not specific to any board or AGESA family.

Change-Id: I26c32fbe8e45018e239762b072dfe3da05271697
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5690
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Kyösti Mälkki 2014-05-05 16:40:15 +03:00
parent 93d9f92cfb
commit 36abdc4017
11 changed files with 133 additions and 65 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/device/Kconfig
View File

@ -191,6 +191,10 @@ config MULTIPLE_VGA_ADAPTERS
bool
default n
config SPD_CACHE
bool
default n
config PCI
bool
default n

2
src/device/Makefile.inc
View File

@ -17,7 +17,7 @@ ramstage-y += smbus_ops.c
romstage-y += device_romstage.c
romstage-$(CONFIG_PCI) += pci_early.c
subdirs-y += oprom
subdirs-y += oprom dram
ramstage-$(CONFIG_VGA_ROM_RUN) += pci_rom.c

1
src/device/dram/Makefile.inc Normal file
View File

@ -0,0 +1 @@
romstage-$(CONFIG_SPD_CACHE) += spd_cache.c ddr3.c

68
src/device/dram/spd_cache.c Normal file
View File

@ -0,0 +1,68 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Advanced Micro Devices, Inc.
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cbfs.h>
#include <console/console.h>
#include <device/dram/ddr3.h>
#include <spd_cache.h>
#include <stdint.h>
#include <string.h>
#define SPD_SIZE 128
#define SPD_CRC_HI 127
#define SPD_CRC_LO 126
int read_spd_from_cbfs(u8 *buf, int idx)
{
const char *spd_file;
size_t spd_file_len = 0;
size_t min_len = (idx + 1) * SPD_SIZE;
printk(BIOS_DEBUG, "read SPD\n");
spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab,
&spd_file_len);
if (!spd_file)
printk(BIOS_EMERG, "file [spd.bin] not found in CBFS");
if (spd_file_len < min_len)
printk(BIOS_EMERG, "Missing SPD data.");
if (!spd_file || spd_file_len < min_len)
return -1;
memcpy(buf, spd_file + (idx * SPD_SIZE), SPD_SIZE);
u16 crc = spd_ddr3_calc_crc(buf, SPD_SIZE);
if (((buf[SPD_CRC_LO] == 0) && (buf[SPD_CRC_HI] == 0))
|| (buf[SPD_CRC_LO] != (crc & 0xff))
|| (buf[SPD_CRC_HI] != (crc >> 8))) {
printk(BIOS_WARNING, "SPD has a invalid or zero-valued CRC\n");
buf[SPD_CRC_LO] = crc & 0xff;
buf[SPD_CRC_HI] = crc >> 8;
u16 i;
printk(BIOS_WARNING, "\nDisplay the SPD");
for (i = 0; i < SPD_SIZE; i++) {
if((i % 16) == 0x00)
printk(BIOS_WARNING, "\n%02x: ", i);
printk(BIOS_WARNING, "%02x ", buf[i]);
}
printk(BIOS_WARNING, "\n");
}
return 0;
}

30
src/include/spd_cache.h Normal file
View File

@ -0,0 +1,30 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _SPD_CACHE_H_
#define _SPD_CACHE_H_
#include <stdint.h>
#if IS_ENABLED(CONFIG_SPD_CACHE)
int read_spd_from_cbfs(u8 *buf, int idx);
#else
static inline int read_spd_from_cbfs(u8 *buf, int idx) { return -1; }
#endif
#endif

60
src/mainboard/gizmosphere/gizmo/BiosCallOuts.c
View File

@ -2,7 +2,6 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -24,13 +23,6 @@
#include "heapManager.h"
#include "SB800.h"
#include <stdlib.h>
#include <cbfs.h>
#include <string.h>
#include <device/dram/ddr3.h>
#define SPD_SIZE 128
#define SPD_CRC_HI 127
#define SPD_CRC_LO 126
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
@ -40,7 +32,7 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
{AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },
{AGESA_LOCATE_BUFFER, agesa_LocateBuffer },
{AGESA_DO_RESET, agesa_Reset },
{AGESA_READ_SPD, BiosReadSpd_from_cbfs },
{AGESA_READ_SPD, agesa_ReadSpd_from_cbfs },
{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
{AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopSuccess },
@ -51,56 +43,6 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
};
const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
AGESA_STATUS BiosReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
#ifdef __PRE_RAM__
AGESA_READ_SPD_PARAMS *info = ConfigPtr;
if (info->MemChannelId > 0)
return AGESA_UNSUPPORTED;
if (info->SocketId != 0)
return AGESA_UNSUPPORTED;
if (info->DimmId != 0)
return AGESA_UNSUPPORTED;
char *spd_file;
size_t spd_file_len;
printk(BIOS_DEBUG, "read SPD\n");
spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab,
&spd_file_len);
if (!spd_file)
die("file [spd.bin] not found in CBFS");
if (spd_file_len < SPD_SIZE)
die("Missing SPD data.");
memcpy((char*)info->Buffer, spd_file, SPD_SIZE);
u16 crc = spd_ddr3_calc_crc(info->Buffer, SPD_SIZE);
if (((info->Buffer[SPD_CRC_LO] == 0) && (info->Buffer[SPD_CRC_HI] == 0))
|| (info->Buffer[SPD_CRC_LO] != (crc & 0xff))
|| (info->Buffer[SPD_CRC_HI] != (crc >> 8))) {
printk(BIOS_WARNING, "SPD has a invalid or zero-valued CRC\n");
info->Buffer[SPD_CRC_LO] = crc & 0xff;
info->Buffer[SPD_CRC_HI] = crc >> 8;
u16 i;
printk(BIOS_WARNING, "\nDisplay the SPD");
for (i = 0; i < SPD_SIZE; i++) {
if((i % 16) == 0x00)
printk(BIOS_WARNING, "\n%02x: ",i);
printk(BIOS_WARNING, "%02x ", info->Buffer[i]);
}
printk(BIOS_WARNING, "\n");
}
Status = AGESA_SUCCESS;
#else
Status = AGESA_UNSUPPORTED;
#endif
return Status;
}
/* Call the host environment interface to provide a user hook opportunity. */
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{

1
src/mainboard/gizmosphere/gizmo/Kconfig
View File

@ -32,6 +32,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048
select GFXUMA
select SPD_CACHE
config MAINBOARD_DIR
string

1
src/mainboard/gizmosphere/gizmo/Makefile.inc
View File

@ -29,7 +29,6 @@ romstage-y += buildOpts.c
romstage-y += agesawrapper.c
romstage-y += BiosCallOuts.c
romstage-y += PlatformGnbPcie.c
romstage-y += ../../../device/dram/ddr3.c
ramstage-y += buildOpts.c
ramstage-y += agesawrapper.c

27
src/northbridge/amd/agesa/def_callouts.c
View File

@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -17,14 +18,15 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cbfs.h>
#include <spd_cache.h>
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "agesawrapper.h"
#include <cbfs.h>
#include "def_callouts.h"
AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
UINTN i;
@ -113,3 +115,24 @@ AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt
return pVbiosImageInfo->ImagePtr == NULL ? AGESA_WARNING : AGESA_SUCCESS;
}
#endif
AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
AGESA_STATUS Status = AGESA_UNSUPPORTED;
#ifdef __PRE_RAM__
AGESA_READ_SPD_PARAMS *info = ConfigPtr;
if (info->MemChannelId > 0)
return AGESA_UNSUPPORTED;
if (info->SocketId != 0)
return AGESA_UNSUPPORTED;
if (info->DimmId != 0)
return AGESA_UNSUPPORTED;
/* Read index 0, first SPD_SIZE bytes of spd.bin file. */
if (read_spd_from_cbfs((u8*)info->Buffer, 0) < 0)
die("No SPD data\n");
Status = AGESA_SUCCESS;
#endif
return Status;
}

2
src/northbridge/amd/agesa/def_callouts.h
View File

@ -65,6 +65,8 @@ AGESA_STATUS agesa_Reset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
AGESA_STATUS agesa_RunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt);
AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr);
AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
typedef struct {

2
src/northbridge/amd/agesa/family14/fam14_callouts.h
View File

@ -26,7 +26,5 @@
/* AGESA ADVANCED CALLOUTS - MEMORY */
AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr);
AGESA_STATUS BiosReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr);
#endif /* CALLOUTS_AMD_AGESA_FAM14_H */