flashrom: Winbond SuperIO SPI driver.
Developed and tested to work on Intel D201GLY in July 2008. Tested by a helpful person on IRC whose name I've since forgotten. Sorry! Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3910 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Peter Stuge
parent
8991302f54
commit
36b3932f99
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@ -34,7 +34,7 @@ OBJS = chipset_enable.o board_enable.o udelay.o jedec.o stm50flw0x0x.o \
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w49f002u.o 82802ab.o pm49fl00x.o sst49lf040.o en29f002a.o \
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sst49lfxxxc.o sst_fwhub.o layout.o cbtable.o flashchips.o physmap.o \
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flashrom.o w39v080fa.o sharplhf00l04.o w29ee011.o spi.o it87spi.o \
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ichspi.o w39v040c.o sb600spi.o
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ichspi.o w39v040c.o sb600spi.o wbsio_spi.o
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all: pciutils dep $(PROGRAM)
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@ -474,7 +474,8 @@ typedef enum {
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BUS_TYPE_ICH9_SPI,
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BUS_TYPE_IT87XX_SPI,
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BUS_TYPE_SB600_SPI,
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BUS_TYPE_VIA_SPI
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BUS_TYPE_VIA_SPI,
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BUS_TYPE_WBSIO_SPI
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} flashbus_t;
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extern flashbus_t flashbus;
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@ -647,6 +648,12 @@ int probe_w29ee011(struct flashchip *flash);
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/* w49f002u.c */
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int write_49f002(struct flashchip *flash, uint8_t *buf);
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/* wbsio_spi.c */
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int wbsio_check_for_spi(const char *name);
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int wbsio_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
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int wbsio_spi_read(struct flashchip *flash, uint8_t *buf);
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int wbsio_spi_write(struct flashchip *flash, uint8_t *buf);
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/* stm50flw0x0x.c */
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int probe_stm50flw0x0x(struct flashchip *flash);
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int erase_stm50flw0x0x(struct flashchip *flash);
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@ -44,6 +44,8 @@ int spi_command(unsigned int writecnt, unsigned int readcnt,
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return ich_spi_command(writecnt, readcnt, writearr, readarr);
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case BUS_TYPE_SB600_SPI:
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return sb600_spi_command(writecnt, readcnt, writearr, readarr);
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case BUS_TYPE_WBSIO_SPI:
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return wbsio_spi_command(writecnt, readcnt, writearr, readarr);
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default:
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printf_debug
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("%s called, but no SPI chipset/strapping detected\n",
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@ -160,6 +162,7 @@ int probe_spi_rdid4(struct flashchip *flash)
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case BUS_TYPE_ICH9_SPI:
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case BUS_TYPE_VIA_SPI:
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case BUS_TYPE_SB600_SPI:
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case BUS_TYPE_WBSIO_SPI:
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return probe_spi_rdid_generic(flash, 4);
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default:
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printf_debug("4b ID not supported on this SPI controller\n");
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@ -229,7 +232,7 @@ int probe_spi_res(struct flashchip *flash)
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uint8_t spi_read_status_register()
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{
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const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR };
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unsigned char readarr[JEDEC_RDSR_INSIZE];
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unsigned char readarr[2]; /* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */
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/* Read Status Register */
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if (flashbus == BUS_TYPE_SB600_SPI) {
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@ -555,6 +558,8 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf)
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case BUS_TYPE_ICH9_SPI:
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case BUS_TYPE_VIA_SPI:
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return ich_spi_read(flash, buf);
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case BUS_TYPE_WBSIO_SPI:
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return wbsio_spi_read(flash, buf);
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default:
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printf_debug
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("%s called, but no SPI chipset/strapping detected\n",
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@ -575,6 +580,8 @@ int spi_chip_write(struct flashchip *flash, uint8_t *buf)
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case BUS_TYPE_ICH9_SPI:
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case BUS_TYPE_VIA_SPI:
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return ich_spi_write(flash, buf);
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case BUS_TYPE_WBSIO_SPI:
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return wbsio_spi_write(flash, buf);
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default:
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printf_debug
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("%s called, but no SPI chipset/strapping detected\n",
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@ -0,0 +1,201 @@
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/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2008 Peter Stuge <peter@stuge.se>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdio.h>
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#include <pci/pci.h>
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#include <stdint.h>
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#include <string.h>
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#include "flash.h"
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#include "spi.h"
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#define WBSIO_PORT1 0x2e
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#define WBSIO_PORT2 0x4e
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static uint16_t wbsio_spibase = 0;
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static uint16_t wbsio_get_spibase(uint16_t port) {
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uint8_t id;
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uint16_t flashport = 0;
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w836xx_ext_enter(port);
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id = wbsio_read(port, 0x20);
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if(id != 0xa0) {
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fprintf(stderr, "\nW83627 not found at 0x%x, id=0x%02x want=0xa0.\n", port, id);
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goto done;
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}
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if (0 == (wbsio_read(port, 0x24) & 2)) {
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fprintf(stderr, "\nW83627 found at 0x%x, but SPI pins are not enabled. (CR[0x24] bit 1=0)\n", port);
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goto done;
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}
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wbsio_write(port, 0x07, 0x06);
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if (0 == (wbsio_read(port, 0x30) & 1)) {
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fprintf(stderr, "\nW83627 found at 0x%x, but SPI is not enabled. (LDN6[0x30] bit 0=0)\n", port);
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goto done;
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}
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flashport = (wbsio_read(port, 0x62) << 8) | wbsio_read(port, 0x63);
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done:
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w836xx_ext_leave(port);
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return flashport;
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}
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int wbsio_check_for_spi(const char *name) {
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if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT1)))
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if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT2)))
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return 1;
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printf_debug("\nwbsio_spibase = 0x%x\n", wbsio_spibase);
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flashbus = BUS_TYPE_WBSIO_SPI;
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return 0;
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}
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/* W83627DHG has 11 command modes:
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* 1=1 command only
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* 2=1 command+1 data write
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* 3=1 command+2 data read
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* 4=1 command+3 address
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* 5=1 command+3 address+1 data write
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* 6=1 command+3 address+4 data write
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* 7=1 command+3 address+1 dummy address inserted by wbsio+4 data read
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* 8=1 command+3 address+1 data read
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* 9=1 command+3 address+2 data read
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* a=1 command+3 address+3 data read
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* b=1 command+3 address+4 data read
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*
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* mode[7:4] holds the command mode
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* mode[3:0] holds SPI address bits [19:16]
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*
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* The Winbond SPI master only supports 20 bit addresses on the SPI bus. :\
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* Would one more byte of RAM in the chip (to get all 24 bits) really make
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* such a big difference?
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*/
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int wbsio_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) {
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int i;
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uint8_t mode = 0;
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printf_debug("%s:", __func__);
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if (1 == writecnt && 0 == readcnt) {
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mode = 0x10;
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} else if (2 == writecnt && 0 == readcnt) {
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OUTB(writearr[1], wbsio_spibase + 4);
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printf_debug(" data=0x%02x", writearr[1]);
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mode = 0x20;
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} else if (1 == writecnt && 2 == readcnt) {
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mode = 0x30;
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} else if (4 == writecnt && 0 == readcnt) {
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printf_debug(" addr=0x%02x", (writearr[1] & 0x0f));
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for (i = 2; i < writecnt; i++) {
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OUTB(writearr[i], wbsio_spibase + i);
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printf_debug("%02x", writearr[i]);
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}
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mode = 0x40 | (writearr[1] & 0x0f);
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} else if (5 == writecnt && 0 == readcnt) {
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printf_debug(" addr=0x%02x", (writearr[1] & 0x0f));
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for (i = 2; i < 4; i++) {
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OUTB(writearr[i], wbsio_spibase + i);
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printf_debug("%02x", writearr[i]);
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}
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OUTB(writearr[i], wbsio_spibase + i);
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printf_debug(" data=0x%02x", writearr[i]);
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mode = 0x50 | (writearr[1] & 0x0f);
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} else if (8 == writecnt && 0 == readcnt) {
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printf_debug(" addr=0x%02x", (writearr[1] & 0x0f));
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for (i = 2; i < 4; i++) {
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OUTB(writearr[i], wbsio_spibase + i);
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printf_debug("%02x", writearr[i]);
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}
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printf_debug(" data=0x");
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for (; i < writecnt; i++) {
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OUTB(writearr[i], wbsio_spibase + i);
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printf_debug("%02x", writearr[i]);
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}
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mode = 0x60 | (writearr[1] & 0x0f);
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} else if (5 == writecnt && 4 == readcnt) {
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/* XXX: TODO not supported by flashrom infrastructure!
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* This mode, 7, discards the fifth byte in writecnt,
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* but since we can not express that in flashrom, fail
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* the operation for now.
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*/
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;
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} else if (4 == writecnt && readcnt >= 1 && readcnt <= 4) {
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printf_debug(" addr=0x%02x", (writearr[1] & 0x0f));
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for (i = 2; i < writecnt; i++) {
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OUTB(writearr[i], wbsio_spibase + i);
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printf_debug("%02x", writearr[i]);
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}
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mode = ((7 + readcnt) << 4) | (writearr[1] & 0x0f);
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}
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printf_debug(" cmd=%02x mode=%02x\n", writearr[0], mode);
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if (!mode) {
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fprintf(stderr, "%s: unsupported command type wr=%d rd=%d\n",
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__func__, writecnt, readcnt);
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return 1;
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}
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OUTB(writearr[0], wbsio_spibase);
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OUTB(mode, wbsio_spibase + 1);
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myusec_delay(10);
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if (!readcnt)
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return 0;
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printf_debug("%s: returning data =", __func__);
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for (i = 0; i < readcnt; i++) {
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readarr[i] = INB(wbsio_spibase + 4 + i);
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printf_debug(" 0x%02x", readarr[i]);
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}
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printf_debug("\n");
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return 0;
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}
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int wbsio_spi_read(struct flashchip *flash, uint8_t *buf) {
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int size = flash->total_size * 1024;
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if (flash->total_size > 1024) {
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fprintf(stderr, "%s: Winbond saved on 4 register bits so max chip size is 1024 KB!\n", __func__);
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return 1;
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}
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memcpy(buf, (const char *)flash->virtual_memory, size);
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return 0;
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}
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int wbsio_spi_write(struct flashchip *flash, uint8_t *buf) {
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int pos, size = flash->total_size * 1024;
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if (flash->total_size > 1024) {
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fprintf(stderr, "%s: Winbond saved on 4 register bits so max chip size is 1024 KB!\n", __func__);
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return 1;
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}
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flash->erase(flash);
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spi_write_enable();
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for (pos = 0; pos < size; pos++) {
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spi_byte_program(pos, buf[pos]);
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while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
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myusec_delay(10);
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}
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spi_write_disable();
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return 0;
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}
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