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mb/google/kahlee: Correct bad gpio entry 

There's no need to set the output enable here; this is already handled
by the native function. I'm making this correction in this change to
prevent the GPIO pin descriptions from getting confusing.

BUG=b:72875858
TEST=Booted, confirmed S5_MUX_CTRL high with and without this change.

Change-Id: I9e047be7169586c59892ef2bdab915683feeebda
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Justin TerAvest 2018-02-20 14:24:36 -07:00 committed by Martin Roth
parent 2e81f394cf
commit 36b568ce7c
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/google/kahlee/variants/baseboard/gpio.c
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@ -91,7 +91,7 @@ const static struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = {
{ GPIO_40, Function0, OUTPUT_H }, { GPIO_40, Function0, OUTPUT_H },
/* GPIO_42 - S5_MUX_CTRL */ /* GPIO_42 - S5_MUX_CTRL */
{ GPIO_42, Function0, OUTPUT_H }, { GPIO_42, Function0, INPUT },
/* GPIO_70 - WLAN_PE_RST_L */ /* GPIO_70 - WLAN_PE_RST_L */
{ GPIO_70, Function0, OUTPUT_H }, { GPIO_70, Function0, OUTPUT_H },