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soc/intel/meteorlake: Add ASPM setting in pcie_rp_config 

This change provides config for devicetree to control ASPM per port

TEST=Build and Boot verified on google/rex

Port of 'commit 6e52c1da4a ("soc/intel/{adl,common}:
Add ASPM setting in pcie_rp_config)'

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I284bf51628193aa5f82f21fbf29c57a6ea5f9cd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70661
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Dinesh Gehlot 2022-12-12 08:48:14 +00:00 committed by Martin L Roth
parent 9f47f958b3
commit 36b6b055bd
1 changed files with 17 additions and 0 deletions
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17
src/soc/intel/meteorlake/fsp_params.c
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@ -93,6 +93,21 @@ static int get_l1_substate_control(enum L1_substates_control ctl)
return ctl - 1; return ctl - 1;
} }
/*
* get_aspm_control() ensures that the right UPD value is set in fsp_params.
* 0: Disable ASPM
* 1: L0s only
* 2: L1 only
* 3: L0s and L1
* 4: Auto configuration
*/
static unsigned int get_aspm_control(enum ASPM_control ctl)
{
if (ctl > ASPM_AUTO)
ctl = ASPM_AUTO;
return ctl;
}
__weak void mainboard_update_soc_chip_config(struct soc_intel_meteorlake_config *config) __weak void mainboard_update_soc_chip_config(struct soc_intel_meteorlake_config *config)
{ {
/* Override settings per board. */ /* Override settings per board. */
@ -393,6 +408,8 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG) s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG)
|| CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); || CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT);
if (rp_cfg->pcie_rp_aspm)
s_cfg->PcieRpAspm[i] = get_aspm_control(rp_cfg->pcie_rp_aspm);
} }
s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
} }