GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel: Move USB PORTSC definition into IA common code 

This patch moves USB Port Status and Control (PORTSC) Reg definition
into IA common code to allow other SoC code to reuse it without
redefining the same for each SoC.

TEST=Able to build and boot google/taeko where USB wake is working.

Change-Id: I6b540eab282403c7a6038916f5982aa26bd631f8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Subrata Banik 2023-03-23 14:48:53 +05:30 committed by Lean Sheng Tan
parent 532e8c059e
commit 36ca7b3104
4 changed files with 24 additions and 43 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
src/soc/intel/alderlake/acpi/xhci.asl
View File

@ -1,18 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <intelblocks/xhci.h>
#include <soc/gpe.h>
#define PORTSCN_OFFSET 0x480
#define PORTSCXUSB3_OFFSET 0x540
#define WAKE_ON_CONNECT_DISCONNECT_ENABLE 0x6000000
/*
* And port status/control reg with RO and RWS bits
* RO bits: 0, 2:3, 10:13, 24, 28:30
* RWS bits: 5:9, 14:16, 25:27
*/
#define RO_BITS_OFF_MASK ~0x80FE0012
/*
* USB Port Wake Enable (UPWE) on usb attach/detach
* Arg0 - Port Number
@ -30,10 +20,8 @@ Method (UPWE, 3, Serialized)
PSCT, 32,
}
Local0 = PSCT
Local0 &= RO_BITS_OFF_MASK
/* Set WCE and WDE bits */
Local0 |= WAKE_ON_CONNECT_DISCONNECT_ENABLE
Local0 &= PORTSCN_BITS_OFF_MASK
Local0 |= PORTSCN_WAKE_ON_BOTH_CONNECT_DISCONNECT_ENABLE
PSCT = Local0
}

17
src/soc/intel/cannonlake/acpi/xhci.asl
View File

@ -1,13 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <intelblocks/xhci.h>
#include <soc/gpe.h>
#define PORTSCN_OFFSET 0x480
#define PORTSCXUSB3_OFFSET 0x540
#define WAKE_ON_CONNECT_DISCONNECT_ENABLE 0x6000000
#define RO_BITS_OFF_MASK ~0x80FE0012
/*
* USB Port Wake Enable (UPWE) on usb attach/detach
* Arg0 - Port Number
@ -25,14 +20,8 @@ Method (UPWE, 3, Serialized)
PSCT, 32,
}
Local0 = PSCT
/*
* And port status/control reg with RO and RWS bits
* RO bits: 0, 2:3, 10:13, 24, 28:30
* RWS bits: 5:9, 14:16, 25:27
*/
Local0 = Local0 & RO_BITS_OFF_MASK
/* Set WCE and WDE bits */
Local0 = Local0 | WAKE_ON_CONNECT_DISCONNECT_ENABLE
Local0 = Local0 & PORTSCN_BITS_OFF_MASK
Local0 = Local0 | PORTSCN_WAKE_ON_BOTH_CONNECT_DISCONNECT_ENABLE
PSCT = Local0
}

16
src/soc/intel/common/block/include/intelblocks/xhci.h
View File

@ -3,6 +3,20 @@
#ifndef SOC_INTEL_COMMON_BLOCK_XHCI_H
#define SOC_INTEL_COMMON_BLOCK_XHCI_H
#define PORTSCN_OFFSET 0x480
#define PORTSCN_WAKE_ON_DISCONNECT_ENABLE 0x4000000
#define PORTSCN_WAKE_ON_CONNECT_ENABLE 0x2000000
/* Set WDE and WCE bits */
#define PORTSCN_WAKE_ON_BOTH_CONNECT_DISCONNECT_ENABLE 0x6000000
/*
* And port status/control reg with RO and RWS bits
* RO bits: 0, 2:3, 10:13, 24, 28:30
* RWS bits: 5:9, 14:16, 25:27
*/
#define PORTSCN_BITS_OFF_MASK ~0x80FE0012
#define PORTSCXUSB3_OFFSET 0x540
#if !defined(__ACPI__)
#include <device/device.h>
#include <device/xhci.h>
#include <elog.h>
@ -63,5 +77,5 @@ const struct xhci_usb_info *soc_get_xhci_usb_info(pci_devfn_t xhci_dev);
*/
void usb_xhci_disable_unused(bool (*ext_usb_xhci_en_cb)(unsigned int port_type,
unsigned int port_id));
#endif /* if !defined(__ACPI__) */
#endif /* SOC_INTEL_COMMON_BLOCK_XHCI_H */

16
src/soc/intel/skylake/acpi/xhci.asl
View File

@ -1,10 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#define PORTSCN_OFFSET 0x480
#define PORTSCXUSB3_OFFSET 0x540
#define WAKE_ON_CONNECT_DISCONNECT_ENABLE 0x6000000
#define RO_BITS_OFF_MASK ~0x80FE0012
#include <intelblocks/xhci.h>
/*
* USB Port Wake Enable (UPWE) on usb attach/detach
@ -23,14 +19,8 @@ Method (UPWE, 3, Serialized)
PSCT, 32,
}
Local0 = PSCT
/*
* And port status/control reg with RO and RWS bits
* RO bits: 0, 2:3, 10:13, 24, 28:30
* RWS bits: 5:9, 14:16, 25:27
*/
Local0 = Local0 & RO_BITS_OFF_MASK
/* Set WCE and WDE bits */
Local0 = Local0 | WAKE_ON_CONNECT_DISCONNECT_ENABLE
Local0 = Local0 & PORTSCN_BITS_OFF_MASK
Local0 = Local0 | PORTSCN_WAKE_ON_BOTH_CONNECT_DISCONNECT_ENABLE
PSCT = Local0
}