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mb/google/nissa/var/joxer: set up gpio 

Set the GPIO configuration of joxer

BUG=b:237628218
TEST=USE="project_joxer emerge-nissa coreboot"

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I1f7529342fc0800878f875d3641a2f93fbe6009a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
This commit is contained in:
Mark Hsieh 2022-06-30 18:01:01 +08:00 committed by Felix Held
parent d3f859d5e5
commit 36f655456b
2 changed files with 104 additions and 0 deletions
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6
src/mainboard/google/brya/variants/joxer/Makefile.inc Normal file
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# SPDX-License-Identifier: GPL-2.0-only
bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-y += gpio.c

98
src/mainboard/google/brya/variants/joxer/gpio.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <commonlib/helpers.h>
#include <soc/gpio.h>
/* Pad configuration in ramstage */
static const struct pad_config override_gpio_table[] = {
/* B5 : SOC_I2C_SUB_SDA ==> NC */
PAD_NC(GPP_B5, NONE),
/* B6 : SOC_I2C_SUB_SCL ==> NC */
PAD_NC(GPP_B6, NONE),
/* D3 : WCAM_RST_L ==> NC */
PAD_NC(GPP_D3, NONE),
/* D15 : EN_PP2800_WCAM_X ==> NC */
PAD_NC(GPP_D15, NONE),
/* D16 : EN_PP1800_PP1200_WCAM_X ==> NC */
PAD_NC(GPP_D16, NONE),
/* E20 : DDP2_CTRLCLK ==> NC */
PAD_NC(GPP_E20, NONE),
/* F6 : CNV_PA_BLANKING ==> NC */
PAD_NC(GPP_F6, NONE),
/* F12 : GSXDOUT ==> NC */
PAD_NC(GPP_F12, NONE),
/* F13 : GSXSLOAD ==> NC */
PAD_NC(GPP_F13, NONE),
/* F15 : GSXSRESET# ==> NC */
PAD_NC(GPP_F15, NONE),
/* H8 : CNV_MFUART2_RXD ==> NC */
PAD_NC(GPP_H8, NONE),
/* H9 : CNV_MFUART2_TXD ==> NC */
PAD_NC(GPP_H9, NONE),
/* H19 : SRCCLKREQ4# ==> NC */
PAD_NC(GPP_H19, NONE),
/* H23 : GPP_H23 ==> NC */
PAD_NC(GPP_H23, NONE),
/* R6 : DMIC_CLK_A_1A ==> NC */
PAD_NC(GPP_R6, NONE),
/* R7 : DMIC_DATA_1A ==> NC */
PAD_NC(GPP_R7, NONE),
};
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* H12 : UART0_RTS# ==> SD_PERST_L */
PAD_CFG_GPO(GPP_H12, 0, DEEP),
/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
PAD_CFG_GPO(GPP_H20, 0, DEEP),
/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
/* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
/* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
/* B11 : PMCALERT# ==> EN_PP3300_WLAN_X */
PAD_CFG_GPO(GPP_B11, 1, DEEP),
/* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
PAD_CFG_GPO(GPP_H13, 1, DEEP),
};
static const struct pad_config romstage_gpio_table[] = {
/* H12 : UART0_RTS# ==> SD_PERST_L */
PAD_CFG_GPO(GPP_H12, 1, DEEP),
/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
PAD_CFG_GPO(GPP_H20, 1, DEEP),
};
const struct pad_config *variant_gpio_override_table(size_t *num)
{
*num = ARRAY_SIZE(override_gpio_table);
return override_gpio_table;
}
const struct pad_config *variant_early_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}
const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(romstage_gpio_table);
return romstage_gpio_table;
}