mainboard/volteer: Enable SaGv for volteer2, delbin & voxel

SaGv needs to be enabled for only QS. On ES2, we are seeing system
instability.

BUG=b:159198381
TEST=Tested for boot. Power and performance tests were run with
volteer2 with qs setup. System showed stability.
Tested for boot stability on on delbin.

Change-Id: I1bce3b9f837fb19ba5a20ae31750a73474a86788
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
This commit is contained in:
Shreesh Chhabbi 2020-06-17 12:40:42 -07:00 committed by Patrick Georgi
parent 8cf43f6c98
commit 370868766b
7 changed files with 9 additions and 2 deletions

View File

@ -47,7 +47,7 @@ chip soc/intel/tigerlake
register "HeciEnabled" = "1"
# FSP configuration
register "SaGv" = "SaGv_Disabled"
register "SaGv" = "SaGv_Enabled"
register "SmbusEnable" = "0"
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0

View File

@ -1,5 +1,4 @@
chip soc/intel/tigerlake
device domain 0 on
end

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@ -15,6 +15,8 @@ chip soc/intel/tigerlake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A / Type-C Port 2
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used
register "SaGv" = "SaGv_Disabled"
device domain 0 on
device pci 15.0 on
chip drivers/i2c/generic

View File

@ -17,6 +17,8 @@ chip soc/intel/tigerlake
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used
register "SaGv" = "SaGv_Disabled"
# I2C Port Config
register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,

View File

@ -17,6 +17,8 @@ chip soc/intel/tigerlake
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used
register "SaGv" = "SaGv_Disabled"
device domain 0 on
device pci 15.0 on
chip drivers/i2c/generic

View File

@ -1,4 +1,5 @@
chip soc/intel/tigerlake
register "SaGv" = "SaGv_Disabled"
device domain 0 on
device pci 15.1 on
chip drivers/i2c/hid

View File

@ -1,4 +1,5 @@
chip soc/intel/tigerlake
register "SaGv" = "SaGv_Disabled"
device domain 0 on
device pci 15.0 on
chip drivers/i2c/generic