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soc/mediatek/mt8195: Update audio and adsp power control 

To control I2S in MT8195 for dojo project, we need to enable adsp
power before audio power. Therefore, we need to update bus protection
steps to correct the setting.

TEST=build pass
BUG=b:204391159
BRANCH=cherry

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Change-Id: I0bcf1ddeebf0d3df0a1d6b22273123be1aaf85a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63106
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Chun-Jie Chen 2022-02-22 14:53:20 +08:00 committed by Hung-Te Lin
parent a6562bd221
commit 3708cb56cb
2 changed files with 16 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
src/soc/mediatek/mt8195/include/soc/spm.h
View File

@ -946,6 +946,7 @@ struct mtk_spm_regs {
check_member(mtk_spm_regs, pwr_status, 0x016c);
check_member(mtk_spm_regs, audio_pwr_con, 0x0358);
check_member(mtk_spm_regs, adsp_pwr_con, 0x0360);
check_member(mtk_spm_regs, ap_mdsrc_req, 0x043c);
check_member(mtk_spm_regs, ulposc_con, 0x644);
@ -999,11 +1000,17 @@ static const struct power_domain_data disp[] = {
};
static const struct power_domain_data audio[] = {
{
.pwr_con = &mtk_spm->adsp_pwr_con,
.pwr_sta_mask = 0x1 << 10,
.sram_pdn_mask = 0x1 << 8,
.sram_ack_mask = 0x1 << 12,
},
{
.pwr_con = &mtk_spm->audio_pwr_con,
.pwr_sta_mask = AUDIO_PWR_STA_MASK,
.sram_pdn_mask = AUDIO_SRAM_PDN_MASK,
.sram_ack_mask = AUDIO_SRAM_ACK_MASK,
.pwr_sta_mask = 0x1 << 8,
.sram_pdn_mask = 0x1 << 8,
.sram_ack_mask = 0x1 << 12,
},
};

7
src/soc/mediatek/mt8195/mtcmos.c
View File

@ -26,7 +26,9 @@ enum {
VDOSYS1_PROT_STEP_2_MASK = 0x00400000,
VDOSYS1_PROT_STEP_1_MASK = 0xC0000000,
AUDIO_PROT_STEP_1_MASK = 0x00000600,
ADSP_PROT_STEP_1_MASK = 0x0001D000,
AUDIO_PROT_STEP_1_MASK = 0x00000A00,
};
void mtcmos_protect_display_bus(void)
@ -72,6 +74,9 @@ void mtcmos_protect_display_bus(void)
void mtcmos_protect_audio_bus(void)
{
write32(&mt8195_infracfg_ao->infra_topaxi_protecten_clr_2,
ADSP_PROT_STEP_1_MASK);
write32(&mt8195_infracfg_ao->infra_topaxi_protecten_clr_2,
AUDIO_PROT_STEP_1_MASK);
}