From 3708f54bb58c9d7a61884cd263f4dfa569e5a14c Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Mon, 24 Apr 2023 18:22:55 -0700
Subject: [PATCH] soc/intel/alderlake: Disable hwp scalibility tracking

Disable scalability tracking for autonomous frequency control in
order to improve power and performance.

BUG=b:280021171
TEST=Boot to OS on brya0

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: If71ee5374c67611b32691bbec4effdf828b3e566
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74723
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
---
 src/soc/intel/alderlake/chipset.cb | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb
index 5d717b8e54..0ab7c8a87a 100644
--- a/src/soc/intel/alderlake/chipset.cb
+++ b/src/soc/intel/alderlake/chipset.cb
@@ -96,6 +96,9 @@ chip soc/intel/alderlake
 	# Disable SaGV reordering operation to start with SaGV point 4 and reduce boot time.
 	register "disable_sagv_reorder" = "true"
 
+	# Disable hwp scalability tracking.
+	register "enable_hwp_scalability_tracking" = "false"
+
 	# NOTE: if any variant wants to override this value, use the same format
 	# as register "common_soc_config.pch_thermal_trip" = "value", instead of
 	# putting it under register "common_soc_config" in overridetree.cb file.