diff --git a/src/Kconfig b/src/Kconfig
index 0b97125c45..ce584f5311 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -693,6 +693,13 @@ config FATAL_ASSERTS
 	help
 	  If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
 
+config HAVE_DEBUG_GPIO
+	bool
+
+config DEBUG_GPIO
+	bool "Output verbose GPIO debug messages"
+	depends on HAVE_DEBUG_GPIO
+
 config DEBUG_CBFS
 	bool "Output verbose CBFS debug messages"
 	default n
diff --git a/src/soc/intel/common/block/gpio/Kconfig b/src/soc/intel/common/block/gpio/Kconfig
index 66cc1822c6..bdbc323c12 100644
--- a/src/soc/intel/common/block/gpio/Kconfig
+++ b/src/soc/intel/common/block/gpio/Kconfig
@@ -1,15 +1,9 @@
 config SOC_INTEL_COMMON_BLOCK_GPIO
 	bool
+	select HAVE_DEBUG_GPIO
 	help
 	  Intel Processor common GPIO support
 
-config DEBUG_SOC_COMMON_BLOCK_GPIO
-	depends on SOC_INTEL_COMMON_BLOCK_GPIO
-	bool "Output verbose GPIO debug messages"
-	default n
-	help
-	  This option enables GPIO debug messages
-
 # Use to program Interrupt Polarity Control (IPCx) register
 # Each bit represents IRQx Active High Polarity Disable configuration:
 # when set to 1, the interrupt polarity associated with IRQx is inverted
diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c
index bd124775b6..9b6ca7e1d5 100644
--- a/src/soc/intel/common/block/gpio/gpio.c
+++ b/src/soc/intel/common/block/gpio/gpio.c
@@ -265,7 +265,7 @@ static void gpio_configure_pad(const struct pad_config *cfg)
 		soc_pad_conf &= mask[i];
 		soc_pad_conf |= pad_conf & ~mask[i];
 
-		if (IS_ENABLED(CONFIG_DEBUG_SOC_COMMON_BLOCK_GPIO))
+		if (IS_ENABLED(CONFIG_DEBUG_GPIO))
 			printk(BIOS_DEBUG,
 			"gpio_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x"
 			" : 0x%08x]\n",
@@ -533,7 +533,7 @@ void gpio_route_gpe(uint8_t gpe0b, uint8_t gpe0c, uint8_t gpe0d)
 			MISCCFG_GPE0_DW1_MASK |
 			MISCCFG_GPE0_DW0_MASK);
 
-	if (IS_ENABLED(CONFIG_DEBUG_SOC_COMMON_BLOCK_GPIO))
+	if (IS_ENABLED(CONFIG_DEBUG_GPIO))
 		printk(BIOS_DEBUG, "misccfg_mask:%x misccfg_value:%x\n",
 			misccfg_mask, misccfg_value);
 	comm = soc_gpio_get_community(&gpio_communities);
diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig
index fd31e51242..d4ae8054a0 100644
--- a/src/soc/intel/denverton_ns/Kconfig
+++ b/src/soc/intel/denverton_ns/Kconfig
@@ -29,6 +29,7 @@ config CPU_SPECIFIC_OPTIONS
 	select BOOTBLOCK_CONSOLE
 	select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
 	select BOOT_DEVICE_SUPPORTS_WRITES
+	select DEBUG_GPIO
 	select POSTCAR_CONSOLE
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_RESET
@@ -50,7 +51,6 @@ config CPU_SPECIFIC_OPTIONS
 #	select SOC_INTEL_COMMON_BLOCK_SA
 	select SOC_INTEL_COMMON_BLOCK_FAST_SPI
 	select SOC_INTEL_COMMON_BLOCK_GPIO
-	select DEBUG_SOC_COMMON_BLOCK_GPIO
 	select SOC_INTEL_COMMON_BLOCK_PCR
 	select TSC_CONSTANT_RATE
 	select TSC_MONOTONIC_TIMER