mb/google/brox: Fix error in DDR DQS config

The DQS mapping for DIMM idx 6 was discovered to be incorrect to what
was in the schematics.  Correcting the mistake in this CL.

BUG=b:311450057,b:300690448
BRANCH=None
TEST=tested on device and it passed memory training

Change-Id: I21f50e2f5b4fae09725c1c7532636ed1cc1a9043
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79843
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>

src/mainboard/google/brox/variants/baseboard/brox/memory.c

@@ -53,7 +53,7 @@ static const struct mb_cfg baseboard_memcfg = {
 		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
 		.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
 		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
 		.ddr7 = { .dqs0 = 0, .dqs1 = 1 }
 	},