GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Intel Lynx Point: LPC: Unify I/O APIC setup 

Remove local copies of reading and writing I/O APIC registers by
using already available functions.

This change is similar to

    commit db4f875a41
    Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Date:   Tue Jan 31 17:24:12 2012 +0200

        IOAPIC: Divide setup_ioapic() in two parts.

        Reviewed-on: http://review.coreboot.org/300

and

    commit e614353194
    Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Date:   Tue Feb 26 17:24:41 2013 +0200

        Unify setting 82801a/b/c/d IOAPIC ID

        Reviewed-on: http://review.coreboot.org/2532

and uses `io_apic_read()` and `io_apic_write()` too. Define
`ACPI_EN` in the header file `pch.h`.

As commented by Aaron Durbin, a separate `pch_enable_acpi()` is
not needed: “The existing code path *in this file* is about enabling
the io apic.” [1].

[1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c

Change-Id: I6f2559f1d134590f781bd2cb325a9560512285dc
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3182
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Paul Menzel 2013-05-03 12:17:02 +02:00 committed by Alexandru Gagniuc
parent 9c50e6a4a0
commit 373a20c335
2 changed files with 18 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

52
src/southbridge/intel/lynxpoint/lpc.c
View File

@ -43,43 +43,29 @@
typedef struct southbridge_intel_lynxpoint_config config_t; typedef struct southbridge_intel_lynxpoint_config config_t;
static void pch_enable_apic(struct device *dev) /**
{ * Set miscellanous static southbridge features.
int i; *
u32 reg32; * @param dev PCI device with I/O APIC control registers
volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
/* Enable ACPI I/O and power management.
* Set SCI IRQ to IRQ9
*/ */
pci_write_config8(dev, ACPI_CNTL, 0x80); static void pch_enable_ioapic(struct device *dev)
{
u32 reg32;
*ioapic_index = 0; /* Enable ACPI I/O range decode */
*ioapic_data = (2 << 24); pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
set_ioapic_id(IO_APIC_ADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */ /* affirm full set of redirection table entries ("write once") */
*ioapic_index = 1; reg32 = io_apic_read(IO_APIC_ADDR, 0x01);
reg32 = *ioapic_data; io_apic_write(IO_APIC_ADDR, 0x01, reg32);
*ioapic_index = 1;
*ioapic_data = reg32;
*ioapic_index = 0; /*
reg32 = *ioapic_data; * Select Boot Configuration register (0x03) and
printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); * use Processor System Bus (0x01) to deliver interrupts.
if (reg32 != (1 << 25)) */
die("APIC Error\n"); io_apic_write(IO_APIC_ADDR, 0x03, 0x01);
printk(BIOS_SPEW, "Dumping IOAPIC registers\n");
for (i=0; i<3; i++) {
*ioapic_index = i;
printk(BIOS_SPEW, " reg 0x%04x:", i);
reg32 = *ioapic_data;
printk(BIOS_SPEW, " 0x%08x\n", reg32);
}
*ioapic_index = 3; /* Select Boot Configuration register. */
*ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
} }
static void pch_enable_serial_irqs(struct device *dev) static void pch_enable_serial_irqs(struct device *dev)
@ -547,7 +533,7 @@ static void lpc_init(struct device *dev)
pci_write_config16(dev, PCI_COMMAND, 0x000f); pci_write_config16(dev, PCI_COMMAND, 0x000f);
/* IO APIC initialization. */ /* IO APIC initialization. */
pch_enable_apic(dev); pch_enable_ioapic(dev);
pch_enable_serial_irqs(dev); pch_enable_serial_irqs(dev);

1
src/southbridge/intel/lynxpoint/pch.h
View File

@ -236,6 +236,7 @@ unsigned get_gpios(const int *gpio_num_array);
#define PMBASE 0x40 #define PMBASE 0x40
#define ACPI_CNTL 0x44 #define ACPI_CNTL 0x44
#define ACPI_EN (1 << 7)
#define BIOS_CNTL 0xDC #define BIOS_CNTL 0xDC
#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */