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skylake: Apply USB2 and USB3 port enable/disable settings 

The USB port enable/disable settings were never getting applied to
the UPD configuration and so were not getting used by FSP.

BUG=chrome-os-partner:44662
BRANCH=none
TEST=build and boot on glados

Change-Id: I13d4eb901215308de4b59083339832d29ce0049f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4fd83caa8087cc349fa933eafac98c2563f501a4
Original-Change-Id: Ia5fa051782eeb837756a14aecb4aa626d25b2bdb
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/296034
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11547
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2015-08-28 17:21:07 -07:00 committed by Patrick Georgi
parent 15c220dc39
commit 3745c65c83
1 changed files with 9 additions and 11 deletions
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20
src/soc/intel/skylake/chip.c
View File

@ -26,6 +26,7 @@
#include <fsp_util.h> #include <fsp_util.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <soc/ramstage.h> #include <soc/ramstage.h>
#include <string.h>
static void pci_domain_set_resources(device_t dev) static void pci_domain_set_resources(device_t dev)
{ {
@ -69,18 +70,15 @@ struct chip_operations soc_intel_skylake_ops = {
/* UPD parameters to be initialized before SiliconInit */ /* UPD parameters to be initialized before SiliconInit */
void soc_silicon_init_params(SILICON_INIT_UPD *params) void soc_silicon_init_params(SILICON_INIT_UPD *params)
{ {
const struct device *dev; const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
const struct soc_intel_skylake_config *config; const struct soc_intel_skylake_config *config = dev->chip_info;
int i;
/* Set the parameters for SiliconInit */ memcpy(params->SerialIoDevMode, config->SerialIoDevMode,
dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); sizeof(params->SerialIoDevMode));
if (!dev || !dev->chip_info) memcpy(params->PortUsb20Enable, config->PortUsb20Enable,
return; sizeof(params->PortUsb20Enable));
config = dev->chip_info; memcpy(params->PortUsb30Enable, config->PortUsb30Enable,
sizeof(params->PortUsb30Enable));
for (i = 0; i < PchSerialIoIndexMax; i++)
params->SerialIoDevMode[i] = config->SerialIoDevMode[i];
params->SataSalpSupport = config->SataSalpSupport; params->SataSalpSupport = config->SataSalpSupport;
params->SataPortsEnable[0] = config->SataPortsEnable[0]; params->SataPortsEnable[0] = config->SataPortsEnable[0];