skylake: Apply USB2 and USB3 port enable/disable settings
The USB port enable/disable settings were never getting applied to the UPD configuration and so were not getting used by FSP. BUG=chrome-os-partner:44662 BRANCH=none TEST=build and boot on glados Change-Id: I13d4eb901215308de4b59083339832d29ce0049f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4fd83caa8087cc349fa933eafac98c2563f501a4 Original-Change-Id: Ia5fa051782eeb837756a14aecb4aa626d25b2bdb Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/296034 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11547 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -26,6 +26,7 @@
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#include <fsp_util.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include <string.h>
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static void pci_domain_set_resources(device_t dev)
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{
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@ -69,18 +70,15 @@ struct chip_operations soc_intel_skylake_ops = {
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/* UPD parameters to be initialized before SiliconInit */
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void soc_silicon_init_params(SILICON_INIT_UPD *params)
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{
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const struct device *dev;
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const struct soc_intel_skylake_config *config;
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int i;
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const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
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const struct soc_intel_skylake_config *config = dev->chip_info;
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/* Set the parameters for SiliconInit */
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dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
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if (!dev || !dev->chip_info)
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return;
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config = dev->chip_info;
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for (i = 0; i < PchSerialIoIndexMax; i++)
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params->SerialIoDevMode[i] = config->SerialIoDevMode[i];
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memcpy(params->SerialIoDevMode, config->SerialIoDevMode,
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sizeof(params->SerialIoDevMode));
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memcpy(params->PortUsb20Enable, config->PortUsb20Enable,
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sizeof(params->PortUsb20Enable));
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memcpy(params->PortUsb30Enable, config->PortUsb30Enable,
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sizeof(params->PortUsb30Enable));
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params->SataSalpSupport = config->SataSalpSupport;
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params->SataPortsEnable[0] = config->SataPortsEnable[0];
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