mb/google/hatch/moonbuggy: copy PCIe configuration from genesis
The moonbuggy pcie topology is the same as genesis so copy from its device tree and gpios in order to enable these devices. BUG=b:199746414 TEST=lspci Change-Id: I4e916a95047b9f955734f164d7578c520478f5af Signed-off-by: Jeff Chase <jnchase@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Jeff Chase
Patrick Georgi
parent
4a4806fd56
commit
374a8b865c
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@ -9,16 +9,34 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_GPI(GPP_A16, NONE, DEEP),
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/* A18 : LAN_PE_ISOLATE_ODL */
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PAD_CFG_GPO(GPP_A18, 1, DEEP),
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/* A19 : PCH_PCON0_PDB_ODL */
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PAD_CFG_GPO(GPP_A19, 1, DEEP),
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/* A20 : LAN_I350_WAKE# */
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PAD_CFG_GPI_IRQ_WAKE(GPP_A20, NONE, DEEP, LEVEL, INVERT),
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/* A23 : M2_WLAN_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT),
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/* B5 : LAN_CLKREQ_ODL */
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PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
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/* B6 : M2_SSD_CLKREQ_ODL */
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PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
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/* B7 : M2_TPU0_CLKREQ_ODL */
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PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
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/* B8 : CLK_PCIE_REQ3 (not connected) */
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PAD_NC(GPP_B8, NONE),
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/* B9 : M2_TPU1_CLKREQ_ODL */
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PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
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/* B10 : M2_WLAN_CLKREQ_ODL */
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PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
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/* C0 : SMBCLK */
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PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
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/* C1 : SMBDATA */
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PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
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/* C3 : PCH_MBCLK1_R (i350) */
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PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
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/* C4 : PCH_MBDAT1_R (i350) */
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PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
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/* C6: M2_WLAN_WAKE_ODL */
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PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE),
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/* C7 : LAN_WAKE_ODL */
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@ -30,10 +48,14 @@ static const struct pad_config gpio_table[] = {
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/* C15 : WLAN_OFF_L */
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PAD_CFG_GPO(GPP_C15, 1, DEEP),
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/* E2 : EN_PP_MST_OD */
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PAD_CFG_GPO(GPP_E2, 1, DEEP),
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/* E9 : USB_A0_OC_ODL */
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PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
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/* E2 : Not connected */
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PAD_NC(GPP_E2, NONE),
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/* E3 : TPU_RST_PIN40 */
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PAD_CFG_GPO(GPP_E3, 1, DEEP),
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/* E7 : TPU_RST_PIN42 */
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PAD_CFG_GPO(GPP_E7, 1, DEEP),
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/* E9 : PU 10K to PP3300_SOC_A */
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PAD_NC(GPP_E9, NONE),
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/* E10 : USB_A1_OC_ODL */
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PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
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@ -66,6 +88,10 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
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/* H5: PCH_I2C_PCON_SCL */
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PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
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/* H6 : PCH_I2C_TPU_SDA */
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PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
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/* H7 : PCH_I2C_TPU_SCL */
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PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
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/* H22 : PWM_PP3300_BIOZZER */
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PAD_CFG_GPO(GPP_H22, 0, DEEP),
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};
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@ -182,16 +182,58 @@ chip soc/intel/cannonlake
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},
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}"
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# PCIe port 7 for LAN
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# PCIe root port 7 for LAN
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register "PcieRpEnable[6]" = "1"
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register "PcieRpLtrEnable[6]" = "1"
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# PCIe port 11 (x2) for NVMe hybrid storage devices
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register "PcieRpEnable[10]" = "1"
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register "PcieRpLtrEnable[10]" = "1"
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# Uses CLK SRC 0
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register "PcieClkSrcUsage[0]" = "6"
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register "PcieClkSrcClkReq[0]" = "0"
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# PCIe root port 8 for WLAN
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register "PcieRpEnable[7]" = "1"
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register "PcieRpLtrEnable[7]" = "1"
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# Uses CLK SRC 5
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register "PcieClkSrcUsage[5]" = "7"
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register "PcieClkSrcClkReq[5]" = "5"
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# PCIe root port 9 for SSD (PCIe Lanes 11, 12)
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register "PcieRpEnable[8]" = "1"
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register "PcieRpLtrEnable[8]" = "1"
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# RP 9 uses CLK SRC 1
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register "PcieClkSrcUsage[1]" = "8"
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register "PcieClkSrcClkReq[1]" = "1"
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# PCIe root port 10 disabled
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register "PcieRpEnable[9]" = "0"
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# PCIe root port 11 TPU1
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register "PcieRpEnable[10]" = "1"
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register "PcieRpLtrEnable[10]" = "1"
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# RP 11 uses CLK SRC 1
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register "PcieClkSrcUsage[4]" = "10"
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register "PcieClkSrcClkReq[4]" = "4"
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# PCIe root port 12 TPU0
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register "PcieRpEnable[11]" = "1"
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register "PcieRpLtrEnable[11]" = "1"
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# RP 11 uses CLK SRC 1
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register "PcieClkSrcUsage[2]" = "11"
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register "PcieClkSrcClkReq[2]" = "2"
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# PCIe port 13 for i350 NIC (x4)
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register "PcieRpEnable[12]" = "1"
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register "PcieRpLtrEnable[12]" = "1"
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# RP 13 uses CLK SRC 3
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register "PcieClkSrcUsage[3]" = "12"
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# RP 13 does not use a source clock request line
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# NOTE: Any value other than a valid source-clock-request (0-5) is
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# effectively "not connected"
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register "PcieClkSrcClkReq[3]" = "0xFF"
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# Disable the remaining ports 14-16
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register "PcieRpEnable[13]" = "0"
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register "PcieRpEnable[14]" = "0"
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register "PcieRpEnable[15]" = "0"
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# GPIO for SD card detect
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register "sdcard_cd_gpio" = "vSD3_CD_B"
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@ -367,6 +409,7 @@ chip soc/intel/cannonlake
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device i2c 4a on end
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end
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end # I2C #3, Realtek RTD2142.
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device pci 16.0 on end # Management Engine Interface 1
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device pci 19.0 on
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chip drivers/i2c/generic
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register "hid" = ""10EC5682""
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@ -381,9 +424,9 @@ chip soc/intel/cannonlake
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device i2c 1a on end
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end
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end #I2C #4
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device pci 1a.0 on end # eMMC
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device pci 1c.6 on
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chip drivers/net
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device pci 1a.0 off end # eMMC
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device pci 1c.6 on # PCI Root Port 7 (LAN)
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chip drivers/net # RTL8111H Ethernet NIC
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register "customized_leds" = "0x05af"
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register "wake" = "GPE0_DW1_07" # GPP_C7
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register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)"
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@ -393,8 +436,24 @@ chip soc/intel/cannonlake
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register "device_index" = "0"
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device pci 00.0 on end
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end
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end # RTL8111H Ethernet NIC
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device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
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end
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device pci 1c.7 on # PCI Root Port 8 (WLAN)
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register "PcieRpSlotImplemented[7]" = "1" # M.2 Slot
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end
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device pci 1d.0 on # PCI Root Port 9 (TPU)
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register "PcieRpSlotImplemented[8]" = "1" # M.2 Slot
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end
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device pci 1d.1 off end # PCI Root Port 10 (Not connected)
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device pci 1d.2 on end # PCI Root Port 11 (TPU1)
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register "PcieRpSlotImplemented[10]" = "1" # M.2 Slot
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device pci 1d.3 on end # PCI Root Port 12 (TPU0)
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register "PcieRpSlotImplemented[11]" = "1" # M.2 Slot
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device pci 1d.4 on # PCI Root Port 13 (X4 i350 NIC)
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register "PcieRpSlotImplemented[12]" = "0" # Built-in
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end
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device pci 1d.5 on end # PCI Root Port 14 (non-root)
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device pci 1d.6 on end # PCI Root Port 15 (non-root)
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device pci 1d.7 on end # PCI Root Port 16 (non-root)
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device pci 1e.3 off end # GSPI #1
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end
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