soc/sifive/fu540: Switch clock to 1GHz in romstage
Invoke clock_init in romstage for SiFive Unleashed. Change-Id: Ib869762d557e8fdf4c83a53698102df116d80389 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/28602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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@ -13,8 +13,13 @@
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* GNU General Public License for more details.
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*/
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#include <cbmem.h>
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#include <console/console.h>
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#include <console/streams.h>
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#include <console/uart.h>
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#include <program_loading.h>
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#include <soc/clock.h>
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#include <soc/sdram.h>
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void main(void)
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{
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@ -22,5 +27,18 @@ void main(void)
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/* TODO: Follow Section 6.3 (FSBL) of the FU540 manual */
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/*
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* Flush console before changing clock/UART divisor to prevent garbage
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* being printed.
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*/
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console_tx_flush();
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clock_init();
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// re-initialize UART
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#if (IS_ENABLED(CONFIG_CONSOLE_SERIAL))
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uart_init(CONFIG_UART_FOR_CONSOLE);
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#endif
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run_ramstage();
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}
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@ -22,6 +22,7 @@ romstage-y += uart.c
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romstage-y += media.c
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romstage-y += sdram.c
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romstage-y += otp.c
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romstage-y += clock.c
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ramstage-y += uart.c
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ramstage-y += clint.c
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@ -29,6 +30,7 @@ ramstage-y += media.c
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ramstage-y += sdram.c
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ramstage-y += cbmem.c
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ramstage-y += otp.c
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ramstage-y += clock.c
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CPPFLAGS_common += -Isrc/soc/sifive/fu540/include
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@ -121,6 +121,8 @@ static struct prci_ctlr *prci = (void *)FU540_PRCI;
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// 33.33 Mhz after reset
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#define FU540_BASE_FQY 33330
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#if ENV_ROMSTAGE
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static void init_coreclk(void)
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{
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// switch coreclk to input reference frequency before modifying PLL
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@ -178,28 +180,32 @@ static void init_pll_ddr(void)
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write32(&prci->ddrpllcfg1, cfg1);
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}
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int clock_get_coreclk_khz(void)
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#define FU540_UART_DEVICES 2
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#define FU540_UART_REG_DIV 0x18
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#define FU540_UART_DIV_VAL 4
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#define FU540_SPI_DIV 0x00
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#define FU540_SPI_DIV_VAL 4
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static void update_peripheral_clock_dividers(void)
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{
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if (read32(&prci->coreclksel) & PRCI_CORECLK_MASK)
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return FU540_BASE_FQY;
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write32((uint32_t *)(FU540_QSPI0 + FU540_SPI_DIV), FU540_SPI_DIV_VAL);
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write32((uint32_t *)(FU540_QSPI1 + FU540_SPI_DIV), FU540_SPI_DIV_VAL);
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write32((uint32_t *)(FU540_QSPI2 + FU540_SPI_DIV), FU540_SPI_DIV_VAL);
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u32 cfg = read32(&prci->corepllcfg0);
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u32 divr = (cfg & PRCI_COREPLLCFG0_DIVR_MASK)
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>> PRCI_COREPLLCFG0_DIVR_SHIFT;
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u32 divf = (cfg & PRCI_COREPLLCFG0_DIVF_MASK)
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>> PRCI_COREPLLCFG0_DIVF_SHIFT;
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u32 divq = (cfg & PRCI_COREPLLCFG0_DIVQ_MASK)
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>> PRCI_COREPLLCFG0_DIVQ_SHIFT;
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printk(BIOS_SPEW, "clk: r=%d f=%d q=%d\n", divr, divf, divq);
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return FU540_BASE_FQY
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* 2 * (divf + 1)
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/ (divr + 1)
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/ (1ul << divq);
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for (size_t i = 0; i < FU540_UART_DEVICES; i++)
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write32((uint32_t *)(FU540_UART(i) + FU540_UART_REG_DIV), FU540_UART_DIV_VAL);
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}
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void clock_init(void)
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{
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/*
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* Update the peripheral clock dividers of UART, SPI and I2C to safe
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* values as we can't put them in reset before changing frequency.
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*/
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update_peripheral_clock_dividers();
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init_coreclk();
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// put DDR and ethernet in reset
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@ -234,3 +240,25 @@ void clock_init(void)
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for (int i = 0; i < 256; i++)
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asm volatile ("nop");
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}
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#endif
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int clock_get_coreclk_khz(void)
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{
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if (read32(&prci->coreclksel) & PRCI_CORECLK_MASK)
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return FU540_BASE_FQY;
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u32 cfg = read32(&prci->corepllcfg0);
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u32 divr = (cfg & PRCI_COREPLLCFG0_DIVR_MASK)
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>> PRCI_COREPLLCFG0_DIVR_SHIFT;
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u32 divf = (cfg & PRCI_COREPLLCFG0_DIVF_MASK)
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>> PRCI_COREPLLCFG0_DIVF_SHIFT;
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u32 divq = (cfg & PRCI_COREPLLCFG0_DIVQ_MASK)
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>> PRCI_COREPLLCFG0_DIVQ_SHIFT;
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printk(BIOS_SPEW, "clk: r=%d f=%d q=%d\n", divr, divf, divq);
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return FU540_BASE_FQY
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* 2 * (divf + 1)
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/ (divr + 1)
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/ (1ul << divq);
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}
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