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soc/intel/broadwell: Add RMRRs after all DRHDs 

The VT-d architecture specification (Doc. D51397-011, Rev. 3.1) says:

 BIOS implementations must report these remapping structure types in
 numerical order. i.e., All remapping structures of type 0 (DRHD)
 enumerated before remapping structures of type 1 (RMRR), and so forth.

So, update the corresponding code to adhere to the specification.

Change-Id: Ib5ef5e006e590d72bec52e057e9b72150e0e636f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Angel Pons 2020-08-03 12:17:22 +02:00
parent c05a3f86ab
commit 37799b3439
1 changed files with 18 additions and 11 deletions
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29
src/soc/intel/broadwell/acpi.c
View File

@ -435,22 +435,19 @@ static unsigned long acpi_fill_dmar(unsigned long current)
const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1; const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1;
/* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */ /* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */
if (igfx_dev && igfx_dev->enabled && gfxvtbar const bool emit_igd =
&& gfxvten && !MCHBAR32(GFXVTBAR + 4)) { igfx_dev && igfx_dev->enabled &&
unsigned long tmp = current; gfxvtbar && gfxvten &&
!MCHBAR32(GFXVTBAR + 4);
/* First, add DRHD entries */
if (emit_igd) {
const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
current += acpi_create_dmar_ds_pci(current, 0, 2, 0); current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
acpi_dmar_drhd_fixup(tmp, current); acpi_dmar_drhd_fixup(tmp, current);
/* Add RMRR entry */
tmp = current;
current += acpi_create_dmar_rmrr(current, 0,
sa_get_gsm_base(), sa_get_tolud_base() - 1);
current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
acpi_dmar_rmrr_fixup(tmp, current);
} }
/* VTVC0BAR has to be set, enabled, and in 32-bit space */ /* VTVC0BAR has to be set, enabled, and in 32-bit space */
@ -468,6 +465,16 @@ static unsigned long acpi_fill_dmar(unsigned long current)
acpi_dmar_drhd_fixup(tmp, current); acpi_dmar_drhd_fixup(tmp, current);
} }
/* Then, add RMRR entries after all DRHD entries */
if (emit_igd) {
const unsigned long tmp = current;
current += acpi_create_dmar_rmrr(current, 0,
sa_get_gsm_base(), sa_get_tolud_base() - 1);
current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
acpi_dmar_rmrr_fixup(tmp, current);
}
return current; return current;
} }