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SB700/SP5100: This configures the HPET clock period. 

Prior to this change the setting would be zeroes and
would cause a BSOD in 64 bit versions of Windows.

Change-Id: I2d422ef9667457af53f9fd055799e489ed2b25db
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1475
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
This commit is contained in:
Dave Frodin 2012-08-21 16:51:33 -06:00 committed by Anton Kochkov
parent cc6019879d
commit 3780597cc3
1 changed files with 8 additions and 0 deletions
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8
src/southbridge/amd/sb700/early_setup.c
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@ -420,6 +420,14 @@ static void sb700_devices_por_init(void)
byte |= 0x24; byte |= 0x24;
pci_write_config8(dev, 0x62, byte); pci_write_config8(dev, 0x62, byte);
/* Configure HPET Counter CLK period */
byte = pci_read_config8(dev, 0x43);
byte &= 0xF7; /* unhide HPET regs */
pci_write_config8(dev, 0x43, byte);
pci_write_config32(dev, 0x34, 0x0429B17E ); /* Counter CLK period */
byte |= 0x08; /* hide HPET regs */
pci_write_config8(dev, 0x43, byte);
/* Features Enable */ /* Features Enable */
pci_write_config32(dev, 0x64, 0x829E79BF); /* bit10: Enables the HPET interrupt. */ pci_write_config32(dev, 0x64, 0x829E79BF); /* bit10: Enables the HPET interrupt. */