From 37a55d16fc1002313392e63e33ca275a5c47238d Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 30 May 2022 18:11:12 +0000
Subject: [PATCH] soc/intel/common/cpu: Use SoC overrides to set CPU privilege
 level
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This patch implements a SoC overrides to set CPU privilege level
as the MSR is not consistent across platforms. For example:
On APL/GLK/DNV, it's MSR 0x120 and CNL onwards it's MSR 0x151.

BUG=b:233199592
TEST=Build and boot google/taeko to ChromeOS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4584516102560e6bb2a4ae8c0d036be40ed96990
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
---
 src/soc/intel/alderlake/cpu.c                    |  9 +++++++++
 src/soc/intel/apollolake/cpu.c                   |  9 +++++++++
 src/soc/intel/cannonlake/cpu.c                   |  9 +++++++++
 .../common/block/include/intelblocks/cpulib.h    |  3 +++
 src/soc/intel/denverton_ns/cpu.c                 |  9 +++++++++
 src/soc/intel/elkhartlake/cpu.c                  |  9 +++++++++
 src/soc/intel/icelake/cpu.c                      |  9 +++++++++
 src/soc/intel/jasperlake/cpu.c                   |  9 +++++++++
 src/soc/intel/skylake/cpu.c                      | 16 ++++++++++++++++
 src/soc/intel/tigerlake/cpu.c                    |  9 +++++++++
 src/soc/intel/xeon_sp/cpx/cpu.c                  |  5 +++++
 src/soc/intel/xeon_sp/skx/cpu.c                  |  5 +++++
 12 files changed, 101 insertions(+)

diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c
index fc4ca61f2d..a6175ed796 100644
--- a/src/soc/intel/alderlake/cpu.c
+++ b/src/soc/intel/alderlake/cpu.c
@@ -38,6 +38,15 @@ bool cpu_soc_is_in_untrusted_mode(void)
 	return !!(msr.lo & ENABLE_IA_UNTRUSTED);
 }
 
+void cpu_soc_bios_done(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(MSR_BIOS_DONE);
+	msr.lo |= ENABLE_IA_UNTRUSTED;
+	wrmsr(MSR_BIOS_DONE, msr);
+}
+
 static void soc_fsp_load(void)
 {
 	fsps_load();
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index 79a69f518c..ec262f7b35 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -54,6 +54,15 @@ bool cpu_soc_is_in_untrusted_mode(void)
 	return !!(msr.lo & ENABLE_IA_UNTRUSTED);
 }
 
+void cpu_soc_bios_done(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(MSR_POWER_MISC);
+	msr.lo |= ENABLE_IA_UNTRUSTED;
+	wrmsr(MSR_POWER_MISC, msr);
+}
+
 void soc_core_init(struct device *cpu)
 {
 	/* Configure Core PRMRR for SGX. */
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c
index b7ca2b4db3..7e5e4cc0ca 100644
--- a/src/soc/intel/cannonlake/cpu.c
+++ b/src/soc/intel/cannonlake/cpu.c
@@ -27,6 +27,15 @@ bool cpu_soc_is_in_untrusted_mode(void)
 	return !!(msr.lo & ENABLE_IA_UNTRUSTED);
 }
 
+void cpu_soc_bios_done(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(MSR_BIOS_DONE);
+	msr.lo |= ENABLE_IA_UNTRUSTED;
+	wrmsr(MSR_BIOS_DONE, msr);
+}
+
 static void soc_fsp_load(void)
 {
 	fsps_load();
diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h
index b9c3ab70c3..281c9651a1 100644
--- a/src/soc/intel/common/block/include/intelblocks/cpulib.h
+++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h
@@ -120,6 +120,9 @@ void cpu_set_eist(bool eist_status);
  */
 bool cpu_soc_is_in_untrusted_mode(void);
 
+/* SoC function to set the BIOS DONE MSR. */
+void cpu_soc_bios_done(void);
+
 /*
  * This function fills in the number of Cores(physical) and Threads(virtual)
  * of the CPU in the function arguments. It also returns if the number of cores
diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c
index 93657fec02..8b5fb40e3c 100644
--- a/src/soc/intel/denverton_ns/cpu.c
+++ b/src/soc/intel/denverton_ns/cpu.c
@@ -31,6 +31,15 @@ bool cpu_soc_is_in_untrusted_mode(void)
 	return !!(msr.lo & ENABLE_IA_UNTRUSTED);
 }
 
+void cpu_soc_bios_done(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(MSR_POWER_MISC);
+	msr.lo |= ENABLE_IA_UNTRUSTED;
+	wrmsr(MSR_POWER_MISC, msr);
+}
+
 static struct smm_relocation_attrs relo_attrs;
 
 static void dnv_configure_mca(void)
diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c
index 3e0dae191a..f4baa65fd9 100644
--- a/src/soc/intel/elkhartlake/cpu.c
+++ b/src/soc/intel/elkhartlake/cpu.c
@@ -24,6 +24,15 @@ bool cpu_soc_is_in_untrusted_mode(void)
 	return !!(msr.lo & ENABLE_IA_UNTRUSTED);
 }
 
+void cpu_soc_bios_done(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(MSR_BIOS_DONE);
+	msr.lo |= ENABLE_IA_UNTRUSTED;
+	wrmsr(MSR_BIOS_DONE, msr);
+}
+
 static void soc_fsp_load(void)
 {
 	fsps_load();
diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c
index f503fcd051..37571758cb 100644
--- a/src/soc/intel/icelake/cpu.c
+++ b/src/soc/intel/icelake/cpu.c
@@ -24,6 +24,15 @@ bool cpu_soc_is_in_untrusted_mode(void)
 	return !!(msr.lo & ENABLE_IA_UNTRUSTED);
 }
 
+void cpu_soc_bios_done(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(MSR_BIOS_DONE);
+	msr.lo |= ENABLE_IA_UNTRUSTED;
+	wrmsr(MSR_BIOS_DONE, msr);
+}
+
 static void soc_fsp_load(void)
 {
 	fsps_load();
diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c
index 01cd6acac7..24e5aa79f9 100644
--- a/src/soc/intel/jasperlake/cpu.c
+++ b/src/soc/intel/jasperlake/cpu.c
@@ -24,6 +24,15 @@ bool cpu_soc_is_in_untrusted_mode(void)
 	return !!(msr.lo & ENABLE_IA_UNTRUSTED);
 }
 
+void cpu_soc_bios_done(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(MSR_BIOS_DONE);
+	msr.lo |= ENABLE_IA_UNTRUSTED;
+	wrmsr(MSR_BIOS_DONE, msr);
+}
+
 static void soc_fsp_load(void)
 {
 	fsps_load();
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 3439836f24..26ab2712a9 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -27,6 +27,10 @@
 
 bool cpu_soc_is_in_untrusted_mode(void)
 {
+	/*
+	 * TODO: Add dynamic detection to identify if skylake SoC
+	 * is in coffeelake board.
+	 */
 	if (!CONFIG(MAINBOARD_SUPPORTS_COFFEELAKE_CPU))
 		return false;
 
@@ -35,6 +39,18 @@ bool cpu_soc_is_in_untrusted_mode(void)
 	return !!(msr.lo & ENABLE_IA_UNTRUSTED);
 }
 
+void cpu_soc_bios_done(void)
+{
+	if (!CONFIG(MAINBOARD_SUPPORTS_COFFEELAKE_CPU))
+		return;
+
+	msr_t msr;
+
+	msr = rdmsr(MSR_BIOS_DONE);
+	msr.lo |= ENABLE_IA_UNTRUSTED;
+	wrmsr(MSR_BIOS_DONE, msr);
+}
+
 static void configure_misc(void)
 {
 	config_t *conf = config_of_soc();
diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c
index ffccdccf44..e81a655329 100644
--- a/src/soc/intel/tigerlake/cpu.c
+++ b/src/soc/intel/tigerlake/cpu.c
@@ -30,6 +30,15 @@ bool cpu_soc_is_in_untrusted_mode(void)
 	return !!(msr.lo & ENABLE_IA_UNTRUSTED);
 }
 
+void cpu_soc_bios_done(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(MSR_BIOS_DONE);
+	msr.lo |= ENABLE_IA_UNTRUSTED;
+	wrmsr(MSR_BIOS_DONE, msr);
+}
+
 static void soc_fsp_load(void)
 {
 	fsps_load();
diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c
index 71249cb1d8..4ecfad0f89 100644
--- a/src/soc/intel/xeon_sp/cpx/cpu.c
+++ b/src/soc/intel/xeon_sp/cpx/cpu.c
@@ -36,6 +36,11 @@ bool cpu_soc_is_in_untrusted_mode(void)
 	return false;
 }
 
+void cpu_soc_bios_done(void)
+{
+	/* IA_UNTRUSTED_MODE is not supported in Cooper Lake */
+}
+
 static void xeon_configure_mca(void)
 {
 	msr_t msr;
diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c
index c29952916a..027e9bbcd3 100644
--- a/src/soc/intel/xeon_sp/skx/cpu.c
+++ b/src/soc/intel/xeon_sp/skx/cpu.c
@@ -26,6 +26,11 @@ bool cpu_soc_is_in_untrusted_mode(void)
 	return false;
 }
 
+void cpu_soc_bios_done(void)
+{
+	/* IA_UNTRUSTED_MODE is not supported in Skylake */
+}
+
 static void xeon_configure_mca(void)
 {
 	msr_t msr;