mb/google/fizz: Add Endeavour variant
Use the existing Karma variant as a base. BUG=b:144307303 TEST=build Change-Id: I09a10e99877d18361b31b36bed703b02508ccd05 Signed-off-by: Jeff Chase <jnchase@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Jeff Chase
Furquan Shaikh
parent
26d1be15ca
commit
37bf996efb
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@ -53,11 +53,13 @@ config MAINBOARD_PART_NUMBER
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string
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string
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default "Fizz" if BOARD_GOOGLE_FIZZ
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default "Fizz" if BOARD_GOOGLE_FIZZ
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default "Karma" if BOARD_GOOGLE_KARMA
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default "Karma" if BOARD_GOOGLE_KARMA
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default "Endeavour" if BOARD_GOOGLE_ENDEAVOUR
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config MAINBOARD_FAMILY
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config MAINBOARD_FAMILY
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string
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string
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default "Google_Fizz" if BOARD_GOOGLE_FIZZ
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default "Google_Fizz" if BOARD_GOOGLE_FIZZ
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default "Google_Kalista" if BOARD_GOOGLE_KARMA
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default "Google_Kalista" if BOARD_GOOGLE_KARMA
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default "Google_Endeavour" if BOARD_GOOGLE_ENDEAVOUR
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config MAX_CPUS
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config MAX_CPUS
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int
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int
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@ -79,6 +81,7 @@ config VARIANT_DIR
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string
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string
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default "fizz" if BOARD_GOOGLE_FIZZ
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default "fizz" if BOARD_GOOGLE_FIZZ
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default "karma" if BOARD_GOOGLE_KARMA
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default "karma" if BOARD_GOOGLE_KARMA
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default "endeavour" if BOARD_GOOGLE_ENDEAVOUR
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config INCLUDE_NHLT_BLOBS
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config INCLUDE_NHLT_BLOBS
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bool "Include blobs for audio."
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bool "Include blobs for audio."
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@ -7,3 +7,7 @@ config BOARD_GOOGLE_FIZZ
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config BOARD_GOOGLE_KARMA
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config BOARD_GOOGLE_KARMA
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bool "-> Karma"
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bool "-> Karma"
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select BOARD_GOOGLE_BASEBOARD_FIZZ
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select BOARD_GOOGLE_BASEBOARD_FIZZ
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config BOARD_GOOGLE_ENDEAVOUR
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bool "-> Endeavour"
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select BOARD_GOOGLE_BASEBOARD_FIZZ
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@ -0,0 +1,4 @@
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bootblock-y += gpio.c
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ramstage-y += gpio.c
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ramstage-y += nhlt.c
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Binary file not shown.
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@ -0,0 +1,232 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2019 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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/* Pad configuration in ramstage */
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/* Leave eSPI pins untouched from default settings */
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static const struct pad_config gpio_table[] = {
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/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP308 */
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/* ESPI_IO0 */
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/* ESPI_IO1 */
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/* ESPI_IO2 */
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/* ESPI_IO3 */
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/* ESPI_CS# */
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/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP331 */
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/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, 20K_PU, DEEP,
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EDGE), /* SD_CDZ */
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/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP329 */
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/* ESPI_CLK */
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/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* TP188 */
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/* PME# */ PAD_CFG_NC(GPP_A11), /* TP149 */
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/* BM_BUSY# */ PAD_CFG_NC(GPP_A12),
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/* SUSWARN# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE,
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DEEP), /* eSPI mode */
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/* ESPI_RESET# */
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/* SUSACK# */ PAD_CFG_NC(GPP_A15), /* TP150 */
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/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
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/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
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/* ISH_GP0 */ PAD_CFG_GPI_APIC(GPP_A18, NONE, DEEP), /* 7322_INTO */
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/* ISH_GP1 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_A19, 1, DEEP, NONE), /* 7322_OE */
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/* ISH_GP2 */ PAD_CFG_GPI_APIC(GPP_A20, NONE, DEEP), /* 7322_INTO */
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/* ISH_GP3 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_A21, 1, DEEP, NONE), /* 7322_OE */
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/* ISH_GP4 */ PAD_CFG_NC(GPP_A22),
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/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),
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/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP156 */
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/* CORE_VID1 */ PAD_CFG_NC(GPP_B1),
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/* VRALERT# */ PAD_CFG_NC(GPP_B2), /* TP152 */
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/* CPU_GP2 */ PAD_CFG_NC(GPP_B3),
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/* CPU_GP3 */ PAD_CFG_NC(GPP_B4),
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/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP,
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NF1), /* CLK_PCIE_LAN_REQ# */
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/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP,
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NF1), /* PCIE_CLKREQ_SSD# */
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/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP,
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NF1), /* PCIE_CLKREQ_TPU# */
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/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP,
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NF1), /* PCIE_CLKREQ_POE# */
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/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP,
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NF1), /* PCIE_CLKREQ_TPU1# */
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/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP,
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NF1), /* PCIE_CLKREQ_WLAN# */
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/* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* MPHY_EXT_PWR */
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/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PM_SLP_S0# */
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/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCI_PLTRST# */
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/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR */
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/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP,
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NF1), /* PCH_SPI_H1_3V3_CS_L */
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/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP,
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NF1), /* PCH_SPI_H1_3V3_CLK */
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/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP,
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NF1), /* PCH_SPI_H1_3V3_MISO */
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/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP,
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NF1), /* PCH_SPI_H1_3V3_MOSI */
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/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP98 */
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/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20),
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/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21),
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/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), /* GSPI1_MOSI */
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/* SML1ALERT# */ PAD_CFG_NC(GPP_B23), /* TP44 */
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/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* PCH_MBCLK0_R */
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/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* PCH_MBDAT0_R */
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/* SMBALERT# */ PAD_CFG_NC(GPP_C2),
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/* SML0CLK */ PAD_CFG_NC(GPP_C3),
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/* SML0DATA */ PAD_CFG_NC(GPP_C4),
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/* SML0ALERT# */ PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1),
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/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU,
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DEEP), /* EC_IN_RW */
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/* SM1DATA */ PAD_CFG_NC(GPP_C7), /* TP99 */
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/* UART0_RXD */ PAD_CFG_NC(GPP_C8),
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/* UART0_TXD */ PAD_CFG_NC(GPP_C9),
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/* UART0_RTS# */ PAD_CFG_NC(GPP_C10),
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/* UART0_CTS# */ PAD_CFG_NC(GPP_C11),
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/* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE,
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DEEP), /* SKU_ID0 */
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/* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE,
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DEEP), /* SKU_ID1 */
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/* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE,
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DEEP), /* SKU_ID2 */
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/* UART1_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE,
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DEEP), /* SKU_ID3 */
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/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* PCH_I2C_TPU_SDA */
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/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* PCH_I2C_TPU_SCL */
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/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* PCH_I2C1_H1_3V3_SDA */
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/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* PCH_I2C1_H1_3V3_SCL */
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/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
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/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
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/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP93 */
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/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE,
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DEEP), /* SCREW_SPI_WP_STATUS */
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/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), /* TP106 */
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/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), /* TP102 */
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/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), /* TP104 */
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/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), /* TP105 */
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/* FASHTRIG */ PAD_CFG_NC(GPP_D4), /* TP91 */
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/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5),
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/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6),
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/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),
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/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),
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/* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE,
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PLTRST, EDGE), /* HP_IRQ_GPIO */
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/* ISH_SPI_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE,
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DEEP), /* OEM_ID1 */
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/* ISH_SPI_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE,
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DEEP), /* OEM_ID2 */
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/* ISH_SPI_MOSI */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE,
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DEEP), /* OEM_ID3 */
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/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13),
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/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),
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/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15),
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/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16),
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/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17),
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/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18),
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/* DMIC_CLK0 */ PAD_CFG_NC(GPP_D19), /* TP100 */
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/* DMIC_DATA0 */ PAD_CFG_NC(GPP_D20), /* TP90 */
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/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), /* TP101 */
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/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22), /* TP94 */
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/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* I2S_MCLK */
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/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE,
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PLTRST), /* H1_PCH_INT_ODL */
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/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP,
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NF1), /* MB_PCIE_SATA#_DET */
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/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2),
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/* CPU_GP0 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_E3, 0, DEEP,
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NONE), /* TPU_RST_PIN40 */
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/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* TP103 */
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/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */
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/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* DEVSLP2_DB */
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/* CPU_GP1 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_E7, 0, DEEP,
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NONE), /* TPU_RST_PIN42 */
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/* SATALED# */ PAD_CFG_NC(GPP_E8), /* TP96 */
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/* USB2_OCO# */ PAD_CFG_NC(GPP_E9), /* T1037 */
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/* USB2_OC1# */ PAD_CFG_NC(GPP_E10), /* T1025 */
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/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP,
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NF1), /* Rear Dual-Stack USB Ports */
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/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP,
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NF1), /* Rear Single USB Port */
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/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP,
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NF1), /* DDI1_HDMI_HPD */
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/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP,
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NF1), /* DDI2_HDMI_HPD */
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/* DDPD_HPD2 */ PAD_CFG_GPI_APIC(GPP_E15, NONE, DEEP), /* PCH_TYPEC_UPFB */
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/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP1021 */
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/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
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/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_DDCCLK_SW */
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/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* HDMI_DDCCLK_DATA */
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/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDI2_DDCCLK_SW */
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/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDI2_DDCDATA_SW */
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/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22),
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/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23),
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/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), /* TP43 */
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/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), /* TP48 */
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/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), /* TP42 */
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/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), /* TP37 */
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/* I2C2_SDA */ PAD_CFG_NC(GPP_F4),
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/* I2C2_SCL */ PAD_CFG_NC(GPP_F5),
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/* I2C3_SDA */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* DDI1_I2C_7322_SDA */
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/* I2C3_SCL */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* DDI1_I2C_7322_SCL */
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/* I2C4_SDA */ PAD_CFG_NC(GPP_F8),
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/* I2C4_SCL */ PAD_CFG_NC(GPP_F9),
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/* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP,
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NF1), /* PCH_I2C2_AUDIO_1V8_SDA */
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/* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP,
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NF1), /* PCH_I2C2_AUDIO_1V8_SCL */
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/* EMMC_CMD */ PAD_CFG_NC(GPP_F12),
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/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13),
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/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14),
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/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15),
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/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16),
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/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17),
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/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18),
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/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19),
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/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20),
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||||||
|
/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21),
|
||||||
|
/* EMMC_CLK */ PAD_CFG_NC(GPP_F22),
|
||||||
|
/* RSVD */ PAD_CFG_NC(GPP_F23),
|
||||||
|
|
||||||
|
/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
|
||||||
|
/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
|
||||||
|
/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
|
||||||
|
/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
|
||||||
|
/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
|
||||||
|
/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CDZ */
|
||||||
|
/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
|
||||||
|
/* SD_WP */ PAD_CFG_NC(GPP_G7), /* TP40 */
|
||||||
|
|
||||||
|
/* BATLOW# */ PAD_CFG_NC(GPD0), /* TP23 */
|
||||||
|
/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* PCH_ACPRESENT */
|
||||||
|
/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE# */
|
||||||
|
/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), /* PCH_PWRBTN# */
|
||||||
|
/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S3# */
|
||||||
|
/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_S4# */
|
||||||
|
/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP22 */
|
||||||
|
/* RSVD */ PAD_CFG_NC(GPD7),
|
||||||
|
/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUS_CLK */
|
||||||
|
/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP83 */
|
||||||
|
/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP84 */
|
||||||
|
/* LANPHYC */ PAD_CFG_NC(GPD11),
|
||||||
|
};
|
||||||
|
|
||||||
|
const struct pad_config *variant_gpio_table(size_t *num)
|
||||||
|
{
|
||||||
|
*num = ARRAY_SIZE(gpio_table);
|
||||||
|
return gpio_table;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,16 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright 2019 Google LLC
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <baseboard/acpi/dptf.asl>
|
||||||
|
|
@ -0,0 +1,21 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright 2019 Google LLC
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __MAINBOARD_EC_H__
|
||||||
|
#define __MAINBOARD_EC_H__
|
||||||
|
|
||||||
|
#include <baseboard/ec.h>
|
||||||
|
|
||||||
|
#endif /* __MAINBOARD_EC_H__ */
|
||||||
|
|
@ -0,0 +1,21 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright 2019 Google LLC
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __MAINBOARD_GPIO_H__
|
||||||
|
#define __MAINBOARD_GPIO_H__
|
||||||
|
|
||||||
|
#include <baseboard/gpio.h>
|
||||||
|
|
||||||
|
#endif /* __MAINBOARD_GPIO_H__ */
|
||||||
|
|
@ -0,0 +1,27 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright 2019 Google LLC
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
#include <baseboard/variants.h>
|
||||||
|
#include <console/console.h>
|
||||||
|
#include <nhlt.h>
|
||||||
|
#include <soc/nhlt.h>
|
||||||
|
|
||||||
|
void variant_nhlt_oem_overrides(const char **oem_id,
|
||||||
|
const char **oem_table_id,
|
||||||
|
uint32_t *oem_revision)
|
||||||
|
{
|
||||||
|
*oem_id = "GOOGLE";
|
||||||
|
*oem_table_id = "ENDEAVOUR";
|
||||||
|
*oem_revision = 0;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,141 @@
|
||||||
|
chip soc/intel/skylake
|
||||||
|
|
||||||
|
# Enable Root port 9(x4) for i350 LAN
|
||||||
|
register "PcieRpEnable[8]" = "1"
|
||||||
|
# Disable CLKREQ#
|
||||||
|
register "PcieRpClkReqSupport[8]" = "0"
|
||||||
|
# RP 9, Enable Advanced Error Reporting
|
||||||
|
register "PcieRpAdvancedErrorReporting[8]" = "1"
|
||||||
|
# RP 9, Enable Latency Tolerance Reporting Mechanism
|
||||||
|
register "PcieRpLtrEnable[8]" = "1"
|
||||||
|
# RP 9 uses uses CLK SRC 2
|
||||||
|
register "PcieRpClkSrcNumber[8]" = "2"
|
||||||
|
|
||||||
|
# These are part of Root port 9(x4)
|
||||||
|
register "PcieRpEnable[9]" = "0"
|
||||||
|
register "PcieRpEnable[10]" = "0"
|
||||||
|
register "PcieRpEnable[11]" = "0"
|
||||||
|
|
||||||
|
register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)" # Type-C
|
||||||
|
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # HDMI
|
||||||
|
register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Rear
|
||||||
|
register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A Rear
|
||||||
|
register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-A Rear
|
||||||
|
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # HDMI Audio
|
||||||
|
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
|
||||||
|
register "usb2_ports[7]" = "USB2_PORT_EMPTY" # None
|
||||||
|
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # H1 (disconnected)
|
||||||
|
|
||||||
|
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
|
||||||
|
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # HDMI
|
||||||
|
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Rear
|
||||||
|
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Rear
|
||||||
|
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Rear
|
||||||
|
register "usb3_ports[5]" = "USB3_PORT_EMPTY" # None
|
||||||
|
|
||||||
|
register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # TPU
|
||||||
|
register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM
|
||||||
|
register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" # None
|
||||||
|
register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" # HDMI
|
||||||
|
register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Audio
|
||||||
|
|
||||||
|
register "SerialIoDevMode" = "{
|
||||||
|
[PchSerialIoIndexI2C0] = PchSerialIoPci,
|
||||||
|
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
|
||||||
|
[PchSerialIoIndexI2C2] = PchSerialIoPci,
|
||||||
|
[PchSerialIoIndexI2C3] = PchSerialIoPci,
|
||||||
|
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
|
||||||
|
[PchSerialIoIndexI2C5] = PchSerialIoPci,
|
||||||
|
[PchSerialIoIndexSpi0] = PchSerialIoPci,
|
||||||
|
[PchSerialIoIndexSpi1] = PchSerialIoDisabled,
|
||||||
|
[PchSerialIoIndexUart0] = PchSerialIoSkipInit,
|
||||||
|
[PchSerialIoIndexUart1] = PchSerialIoDisabled,
|
||||||
|
[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
|
||||||
|
}"
|
||||||
|
|
||||||
|
device domain 0 on
|
||||||
|
device pci 14.0 on
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
device usb 0.0 on
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB2 HDMI In""
|
||||||
|
register "type" = "UPC_TYPE_INTERNAL"
|
||||||
|
device usb 2.1 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB2 Type-A Rear Left""
|
||||||
|
register "type" = "UPC_TYPE_A"
|
||||||
|
device usb 2.2 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB2 Type-A Rear Middle""
|
||||||
|
register "type" = "UPC_TYPE_A"
|
||||||
|
device usb 2.3 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB2 Type-A Rear Right""
|
||||||
|
register "type" = "UPC_TYPE_A"
|
||||||
|
device usb 2.4 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB2 HDMI Audio In""
|
||||||
|
register "type" = "UPC_TYPE_INTERNAL"
|
||||||
|
device usb 2.5 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB3 HDMI Video In""
|
||||||
|
register "type" = "UPC_TYPE_INTERNAL"
|
||||||
|
device usb 3.1 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB3 Type-A Rear Left""
|
||||||
|
register "type" = "UPC_TYPE_USB3_A"
|
||||||
|
device usb 3.2 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB3 Type-A Rear Middle""
|
||||||
|
register "type" = "UPC_TYPE_USB3_A"
|
||||||
|
device usb 3.3 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB3 Type-A Rear Right""
|
||||||
|
register "type" = "UPC_TYPE_USB3_A"
|
||||||
|
device usb 3.4 on end
|
||||||
|
end
|
||||||
|
device usb 3.5 off end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end # USB xHCI
|
||||||
|
device pci 15.3 on
|
||||||
|
chip drivers/i2c/generic
|
||||||
|
register "hid" = "ACPI_DT_NAMESPACE_HID"
|
||||||
|
register "desc" = ""Chrontel 7322""
|
||||||
|
register "uid" = "1"
|
||||||
|
register "compat_string" = ""chrontel,7322""
|
||||||
|
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_HIGH(GPP_A18)"
|
||||||
|
device i2c 75 on end
|
||||||
|
end
|
||||||
|
chip drivers/i2c/generic
|
||||||
|
register "hid" = "ACPI_DT_NAMESPACE_HID"
|
||||||
|
register "desc" = ""Chrontel 7322""
|
||||||
|
register "uid" = "2"
|
||||||
|
register "compat_string" = ""chrontel,7322""
|
||||||
|
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_HIGH(GPP_A20)"
|
||||||
|
device i2c 76 on end
|
||||||
|
end
|
||||||
|
end # I2C #3
|
||||||
|
device pci 19.1 on
|
||||||
|
chip drivers/i2c/generic
|
||||||
|
register "hid" = ""10EC5663""
|
||||||
|
register "name" = ""RT53""
|
||||||
|
register "desc" = ""Realtek RT5663""
|
||||||
|
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)"
|
||||||
|
device i2c 13 on end
|
||||||
|
end
|
||||||
|
end # I2C #5
|
||||||
|
device pci 1d.0 on end # PCI Express Port 9 for POE LAN
|
||||||
|
device pci 1d.1 off end # PCI Express Port 10
|
||||||
|
device pci 1d.2 off end # PCI Express Port 11
|
||||||
|
device pci 1d.3 off end # PCI Express Port 12
|
||||||
|
end
|
||||||
|
end
|
||||||
Loading…
Reference in New Issue