soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating

The patch adds mechanism in the Alder Lake SoC code to control PCH
USB2 Phy power gating from brya board variant's devicetree. Please refer
Intel doc#723158 for more information.

BUG=b:221461379
TEST=Build and boot Gimble board

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I3d80a3e36c6f8a3c0f174f955b11457752809f4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>

src/soc/intel/alderlake/chip.h

@@ -573,6 +573,13 @@ struct soc_intel_alderlake_config {
 	 * Default 0. Set this to 1 in order to disable C state demotion.
 	 */
 	bool disable_c1_state_auto_demotion;
+
+	/*
+	 * Enable or Disable PCH USB2 Phy power gating.
+	 * Default 0. Set this to 1 in order to disable PCH USB2 Phy Power gating.
+	 * Workaround for Intel TA# 723158 to prevent possible display flicker.
+	 */
+	bool usb2_phy_sus_pg_disable;
 };
 
 typedef struct soc_intel_alderlake_config config_t;

src/soc/intel/alderlake/fsp_params.c

@@ -500,6 +500,8 @@ static void fill_fsps_xhci_params(FSP_S_CONFIG *s_cfg,
 		if (config->tcss_ports[i].enable)
 			s_cfg->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin;
 	}
+
+	s_cfg->PmcUsb2PhySusPgEnable = !config->usb2_phy_sus_pg_disable;
 }
 
 static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg,