From 37cae540343d8f02258c3209f90114e7189753e2 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Tue, 2 Feb 2021 16:28:07 +0100
Subject: [PATCH] nb/intel/x/bootblock.c Revert `include <arch/pci_io_cfg.h>`

This partially reverts:

- Commit 77d3b655ed
- Commit 487c1a24f5
- Commit 875c21f491
- Commit c4d1b47ad9
- Commit b96c358751
- Commit 9cbf26d18e

It is intentional to use <device/pci_ops.h> whenever one needs to use
PCI config access. The bootblock.c files needing I/O config do not need
to be an exception to this.

Change-Id: Ifba05717dad404a844618815c5347a05e07a3362
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
---
 src/northbridge/intel/gm45/bootblock.c        | 2 +-
 src/northbridge/intel/haswell/bootblock.c     | 2 +-
 src/northbridge/intel/i945/bootblock.c        | 2 +-
 src/northbridge/intel/ironlake/bootblock.c    | 2 +-
 src/northbridge/intel/sandybridge/bootblock.c | 2 +-
 src/northbridge/intel/x4x/bootblock.c         | 2 +-
 6 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c
index e2cabdb166..a9a1e8eb2d 100644
--- a/src/northbridge/intel/gm45/bootblock.c
+++ b/src/northbridge/intel/gm45/bootblock.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/bootblock.h>
-#include <arch/pci_io_cfg.h>
 #include <assert.h>
+#include <device/pci_ops.h>
 #include <types.h>
 
 #include "gm45.h"
diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c
index 0bb8ae2aad..1336582889 100644
--- a/src/northbridge/intel/haswell/bootblock.c
+++ b/src/northbridge/intel/haswell/bootblock.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/bootblock.h>
-#include <arch/pci_io_cfg.h>
 #include <assert.h>
+#include <device/pci_ops.h>
 #include <types.h>
 
 #include "haswell.h"
diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c
index edb9a8d4d0..448d5e411a 100644
--- a/src/northbridge/intel/i945/bootblock.c
+++ b/src/northbridge/intel/i945/bootblock.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/bootblock.h>
-#include <arch/pci_io_cfg.h>
 #include <assert.h>
+#include <device/pci_ops.h>
 #include <types.h>
 
 #include "i945.h"
diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c
index 02b63a64b3..6610a3e38c 100644
--- a/src/northbridge/intel/ironlake/bootblock.c
+++ b/src/northbridge/intel/ironlake/bootblock.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/bootblock.h>
-#include <arch/pci_io_cfg.h>
 #include <assert.h>
+#include <device/pci_ops.h>
 #include <types.h>
 
 #include "ironlake.h"
diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c
index 92f9aeee49..1eba74438c 100644
--- a/src/northbridge/intel/sandybridge/bootblock.c
+++ b/src/northbridge/intel/sandybridge/bootblock.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/bootblock.h>
-#include <arch/pci_io_cfg.h>
 #include <assert.h>
+#include <device/pci_ops.h>
 #include <types.h>
 
 #include "sandybridge.h"
diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c
index aedcdd9089..f15d181354 100644
--- a/src/northbridge/intel/x4x/bootblock.c
+++ b/src/northbridge/intel/x4x/bootblock.c
@@ -2,8 +2,8 @@
 
 #include <arch/bootblock.h>
 #include <arch/mmio.h>
-#include <arch/pci_io_cfg.h>
 #include <assert.h>
+#include <device/pci_ops.h>
 #include <types.h>
 
 #include "x4x.h"