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arch/x86 & commonlib: Add macros for postcodes used in x86/tables 

The 0x9a, 0x9b, and 0x9c postcodes are not used anywhere else in the
coreboot tree other than in arch/x86/tables.c.  Add macros to
standardize these postcodes.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I16be65ffa3f0b253fe4a9bb7bfb97597a760ad3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This commit is contained in:
Martin Roth 2022-11-03 18:20:17 -06:00 committed by Fred Reitberger
parent 605f793af8
commit 37ccb2ce82
2 changed files with 24 additions and 3 deletions
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6
src/arch/x86/tables.c
View File

@ -17,7 +17,7 @@ static unsigned long write_pirq_table(unsigned long rom_table_end)
unsigned long high_table_pointer;
#define MAX_PIRQ_TABLE_SIZE (4 * 1024)
post_code(0x9a);
post_code(POST_X86_WRITE_PIRQ_TABLE);
/* This table must be between 0x0f0000 and 0x100000 */
rom_table_end = write_pirq_routing_table(rom_table_end);
@ -49,7 +49,7 @@ static unsigned long write_mptable(unsigned long rom_table_end)
unsigned long high_table_pointer;
#define MAX_MP_TABLE_SIZE (4 * 1024)
post_code(0x9b);
post_code(POST_X86_WRITE_MPTABLE);
/* The smp table must be in 0-1K, 639K-640K, or 960K-1M */
rom_table_end = write_smp_table(rom_table_end);
@ -78,7 +78,7 @@ static unsigned long write_acpi_table(unsigned long rom_table_end)
unsigned long high_table_pointer;
const size_t max_acpi_size = CONFIG_MAX_ACPI_TABLE_SIZE_KB * KiB;
post_code(0x9c);
post_code(POST_X86_WRITE_ACPITABLE);
/* Write ACPI tables to F segment and high tables area */

21
src/commonlib/include/commonlib/console/post_codes.h
View File

@ -286,6 +286,27 @@
*/
#define POST_FSP_SILICON_EXIT 0x99
/**
* \brief Entry to write_pirq_table
*
* coreboot entered write_pirq_table
*/
#define POST_X86_WRITE_PIRQ_TABLE 0x9a
/**
* \brief Entry to write_mptable
*
* coreboot entered write_mptable
*/
#define POST_X86_WRITE_MPTABLE 0x9b
/**
* \brief Entry to write_acpi_table
*
* coreboot entered write_acpi_table
*/
#define POST_X86_WRITE_ACPITABLE 0x9c
/**
* \brief Before calling FSP Multiphase SiliconInit
*