From 37d4ffb0a56bc127111c9f10ffe31e3a55e133ee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 21 Dec 2018 11:46:09 +0100 Subject: [PATCH] src/mainboard/pcengines/apu1: Enable LPC TPM MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PC Engines apu1 has a 20 pin LPC header that allows connection of external TPM module. Add necessary Kconfig option and devicetree entry for TPM. Change-Id: Ic9f3d41c6e8346a12553386b9c00de6b8fd21abd Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/30354 Reviewed-by: Paul Menzel Reviewed-by: Kyösti Mälkki Reviewed-by: Philipp Deppenwiese Tested-by: build bot (Jenkins) --- src/mainboard/pcengines/apu1/Kconfig | 1 + src/mainboard/pcengines/apu1/devicetree.cb | 3 +++ 2 files changed, 4 insertions(+) diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index 9d4215901f..07aaa8c1b6 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -31,6 +31,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_2048 select GENERIC_SPD_BIN select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS + select MAINBOARD_HAS_LPC_TPM config MAINBOARD_DIR string diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb index 6af6d2e6de..2e8b8f4cfd 100644 --- a/src/mainboard/pcengines/apu1/devicetree.cb +++ b/src/mainboard/pcengines/apu1/devicetree.cb @@ -70,6 +70,9 @@ chip northbridge/amd/agesa/family14/root_complex device pnp 2e.607 off end device pnp 2e.e off end end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end # LPC TPM end #LPC device pci 14.4 on end # PCIB 0x4384 always active; pins remapped to gpio by disconnect_pcib = 1 device pci 14.5 off end # OHCI FS/LS USB