From 3840bcc19e28401e5fd4e3b4c0f0d1438fbbdeed Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Mon, 21 Dec 2020 03:46:58 +0100 Subject: [PATCH] mb/intel/leafhill: do UART pad configuration at board-level MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Thus, add the corresponding pads to the early UART gpio table for the board as a first step. Common UART pad config code then gets dropped in CB:48829. Also switch to `bootblock_mainboard_early_init` to configure the pads in early bootblock before console initialization, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: Ibc727302109456eb1d86652c947ce85b3a64c5b2 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/49436 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/intel/leafhill/bootblock.c | 2 +- src/mainboard/intel/leafhill/brd_gpio_early.h | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/leafhill/bootblock.c b/src/mainboard/intel/leafhill/bootblock.c index 0f3898a140..4cd1e6a4cf 100644 --- a/src/mainboard/intel/leafhill/bootblock.c +++ b/src/mainboard/intel/leafhill/bootblock.c @@ -5,7 +5,7 @@ #include "brd_gpio_early.h" -void bootblock_mainboard_init(void) +void bootblock_mainboard_early_init(void) { gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); } diff --git a/src/mainboard/intel/leafhill/brd_gpio_early.h b/src/mainboard/intel/leafhill/brd_gpio_early.h index e44bc706fa..8b40f53721 100644 --- a/src/mainboard/intel/leafhill/brd_gpio_early.h +++ b/src/mainboard/intel/leafhill/brd_gpio_early.h @@ -12,5 +12,9 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), PAD_CFG_NF(LPC_CLKOUT0, UP_20K, DEEP, NF1), - PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1) + PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1), + + /* UART */ + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX */ + PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX */ };